PIC18LF1330-I/SO Microchip Technology, PIC18LF1330-I/SO Datasheet - Page 42
![IC PIC MCU FLASH 4KX16 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC18LF1330-I/SO
Manufacturer Part Number
PIC18LF1330-I/SO
Description
IC PIC MCU FLASH 4KX16 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
6.PIC18F1230-IP.pdf
(312 pages)
Specifications of PIC18LF1330-I/SO
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
256Byte
Cpu Speed
40MHz
No.
RoHS Compliant
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF1330-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- PIC18F1230-IP PDF datasheet #6
- Current page: 42 of 318
- Download datasheet (3Mb)
PIC18F1230/1330
5.4
PIC18F1230/1330 devices implement a BOR circuit that
provides the user with a number of configuration and
power-saving options. The BOR is controlled by the
BORV1:BORV0 and BOREN1:BOREN0 Configuration
bits. There are a total of four BOR configurations which
are summarized in Table 5-1.
The BOR threshold is set by the BORV1:BORV0 bits.
If BOR is enabled (any values of BOREN1:BOREN0
except ‘00’), any drop of V
D005) for greater than T
the device. A Reset may or may not occur if V
below V
Brown-out Reset until V
If the Power-up Timer is enabled, it will be invoked after
V
Reset
(parameter 33). If V
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once V
Timer will execute the additional time delay.
BOR
independently configured. Enabling Brown-out Reset
does not automatically enable the PWRT.
5.4.1
When BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This is
done with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function as
previously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in this
mode; otherwise it is read as ‘0’.
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
TABLE 5-1:
DS39758D-page 42
DD
BOREN1
BOR Configuration
rises above V
0
0
1
1
and
BOR
for
Brown-out Reset (BOR)
SOFTWARE ENABLED BOR
for less than T
an
the
BOREN0
BOR CONFIGURATIONS
DD
additional
BOR
Power-on
0
1
0
1
DD
rises above V
DD
; it then will keep the chip in
drops below V
BOR
BOR
DD
rises above V
(RCON<6>)
Unavailable
Unavailable
Unavailable
(parameter 35) will reset
SBOREN
below V
Available
Status of
. The chip will remain in
time
Timer
BOR
delay,
BOR
, the Power-up
BOR
(PWRT)
BOR
(parameter
BOR disabled; must be enabled by reprogramming the Configuration bits.
BOR enabled in software; operation controlled by SBOREN.
BOR enabled in hardware in Run and Idle modes, disabled during
Sleep mode.
BOR enabled in hardware; must be disabled by reprogramming the
Configuration bits.
.
while the
DD
T
PWRT
falls
are
change BOR configuration. It also allows the user to
tailor device power consumption in software by
eliminating the incremental current that the BOR
consumes. While the BOR current is typically very
small, it may have some impact in low-power
applications.
5.4.2
When Brown-out Reset is enabled, the BOR bit always
resets to ‘0’ on any Brown-out Reset or Power-on
Reset event. This makes it difficult to determine if a
Brown-out Reset event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR bit is reset to ‘1’ in software
immediately after any Power-on Reset event. If BOR is
‘0’ while POR is ‘1’, it can be reliably assumed that a
Brown-out Reset event has occurred.
5.4.3
When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
Note:
BOR Operation
Even when BOR is under software control,
the Brown-out Reset voltage level is still
set by the BORV1:BORV0 Configuration
bits. It cannot be changed in software.
DETECTING BOR
DISABLING BOR IN SLEEP MODE
2009 Microchip Technology Inc.
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