DSPIC33FJ12MC202-I/SP Microchip Technology, DSPIC33FJ12MC202-I/SP Datasheet - Page 191
![IC DSPIC MCU/DSP 12K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ12MC202-I/SP
Manufacturer Part Number
DSPIC33FJ12MC202-I/SP
Description
IC DSPIC MCU/DSP 12K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
4.DSPIC33FJ12MC202-IML.pdf
(282 pages)
Specifications of DSPIC33FJ12MC202-I/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC24HJ12GP201-ISO PDF datasheet
- DSPIC33FJ12MC201-ISO PDF datasheet #2
- DSPIC33FJ12MC201-ISO PDF datasheet #3
- DSPIC33FJ12MC202-IML PDF datasheet #4
- Current page: 191 of 282
- Download datasheet (4Mb)
REGISTER 19-2:
© 2008 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-11
bit 10
bit 9-8
bit 7
bit 6
bit 5-2
bit 1
bit 0
R/W-0
BUFS
R-0
VCFG<2:0>: Converter Voltage Reference Configuration bits
Unimplemented: Read as ‘0’
CSCNA: Scan Input Selections for CH0+ during Sample A bit
1 = Scan inputs
0 = Do not scan inputs
CHPS<1:0>: Select Channels Utilized bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = ADC is currently filling second half of buffer, user should access data in the first half
0 = ADC is currently filling first half of buffer, user application should access data in the second half
Unimplemented: Read as ‘0’
SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
•
•
•
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
BUFM: Buffer Fill Mode Select bit
1 = Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt
0 = Always starts filling buffer from the beginning
ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample A on first sample and Sample B on next sample
0 = Always uses channel input selects for Sample A
VCFG<2:0>
000
001
010
011
1xx
R/W-0
U-0
—
AD1CON2: ADC1 CONTROL REGISTER 2
External V
External V
ADREF+
AV
AV
AV
W = Writable bit
‘1’ = Bit is set
DD
DD
DD
R/W-0
R/W-0
REF
REF
+
+
External V
External V
ADREF-
AV
AV
AV
R/W-0
Preliminary
U-0
—
SS
SS
SS
SMPI<3:0>
dsPIC33FJ12MC201/202
REF
REF
-
-
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
CSCNA
R/W-0
R/W-0
x = Bit is unknown
R/W-0
R/W-0
BUFM
CHPS<1:0>
DS70265C-page 189
R/W-0
R/W-0
ALTS
bit 8
bit 0
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