AT32UC3L064-ZAUT Atmel, AT32UC3L064-ZAUT Datasheet - Page 476
![IC MCU AVR32 64KB FLASH 48VQFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3L064-ZAUT
Manufacturer Part Number
AT32UC3L064-ZAUT
Description
IC MCU AVR32 64KB FLASH 48VQFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3L-EK.pdf
(858 pages)
Specifications of AT32UC3L064-ZAUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 9 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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21.8.5.2
21.8.6
Figure 21-10. Programmer Sends Data While the Bus is Busy
32099F–11/2010
TWI DATA transfer
(DADR + W + START + Write THR)
Multi-master Mode
TWCK
TWD
Data Receive with the Peripheral DMA Controller
A transfer is programmed
More than one master may access the bus at the same time without data corruption by using
arbitration.
Arbitration starts as soon as two or more masters place information on the bus at the same
time, and stops (arbitration is lost) for the master that intends to send a logical one while the
other master sends a logical zero.
As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order
to detect a STOP. The SR.ARBLST flag will be set. When the STOP is detected, the master
who lost arbitration may reinitiate the data transfer.
Arbitration is illustrated in
If the user starts a transfer and if the bus is busy, TWIM automatically waits for a STOP condi-
tion on the bus before initiating the transfer (see
Note:
3. Start the transfer by setting the Peripheral DMA Controller TXTEN bit.
4. Wait for the Peripheral DMA Controller end TX flag.
5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller
1. Initialize the receive Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
3. Start the transfer by setting the Peripheral DMA Controller RXTEN bit.
4. Wait for the Peripheral DMA Controller end RX flag.
5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller
TXDIS bit.
RXDIS bit.
DATA sent by a master
The state of the bus (busy or free) is not indicated in the user interface.
Bus is busy
STOP sent by the master
Transfer is kept
Figure 21-11 on page
Bus is free
Bus is considered as free
Transfer is initiated
477.
Figure 21-10 on page
START sent by the TWI
AT32UC3L016/32/64
DATA sent by the TWI
476).
476
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