AT32UC3L064-ZAUT Atmel, AT32UC3L064-ZAUT Datasheet - Page 702
![IC MCU AVR32 64KB FLASH 48VQFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3L064-ZAUT
Manufacturer Part Number
AT32UC3L064-ZAUT
Description
IC MCU AVR32 64KB FLASH 48VQFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3L-EK.pdf
(858 pages)
Specifications of AT32UC3L064-ZAUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 9 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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29.4
29.5
29.5.1
29.5.2
29.5.3
29.6
29.6.1
32099F–11/2010
I/O Lines Description
Product Dependencies
Functional Description
I/O Lines
Clocks
Debug Operation
Enabling the Lookup Table Inputs
Table 29-1.
Each LUT have 4 inputs and one output. The inputs and outputs for the LUTs are mapped
sequentially to the inputs and outputs. This means that LUT0 is connected to IN0 to IN3 and
OUT0. LUT1 is connected to IN4 to IN7 and OUT1. In general, LUTn is connected to IN[4n] to
IN[4n+3] and OUTn.
In order to use this module, other parts of the system must be configured correctly, as described
below.
The pins used for interfacing the GLOC may be multiplexed with I/O Controller lines. The pro-
grammer must first program the I/O Controller to assign the desired GLOC pins to their
peripheral function. If I/O lines of the GLOC are not used by the application, they can be used for
other purposes by the I/O Controller.
It is only required to enable the GLOC inputs and outputs actually in use. Pullups for pins config-
ured to be used by the GLOC will be disabled.
The clock for the GLOC bus interface (CLK_GLOC) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the GLOC before disabling the clock, to avoid freezing the module in an undefined state.
Additionally, the GLOC depends on a dedicated Generic Clock (GCLK). The GCLK can be set to
a wide range of frequencies and clock sources, and must be enabled by the System Control
Interface (SCIF) before the GLOC filter can be used.
When an external debugger forces the CPU into debug mode, the GLOC continues normal
operation.
Since the inputs to each lookup table (LUT) unit can be multiplexed with other peripherals, each
input must be explicitly enabled by writing a one to the corresponding enable bit (AEN) in the
corresponding Control Register (CR).
If no inputs are enabled, the output OUTn will be the least significant bit in the TRUTHn register.
Pin Name
IN0-INm
OUT0-OUTn
I/O Lines Description
Output from lookup tables
Pin Description
Inputs to lookup tables
AT32UC3L016/32/64
Type
Input
Output
702
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