AT32UC3L064-ZAUT Atmel, AT32UC3L064-ZAUT Datasheet - Page 479
![IC MCU AVR32 64KB FLASH 48VQFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3L064-ZAUT
Manufacturer Part Number
AT32UC3L064-ZAUT
Description
IC MCU AVR32 64KB FLASH 48VQFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3L-EK.pdf
(858 pages)
Specifications of AT32UC3L064-ZAUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 9 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Figure 21-13. Combining a Read and Write Transfer
21.8.8
21.8.8.1
Figure 21-14. A Write Transfer with 10-bit Addressing
21.8.8.2
32099F–11/2010
SR.IDLE
RXRDY
TXRDY
TWD
RHR
THR
Ten Bit Addressing
S
Master Transmitter
Master Receiver
SADR
S
1
R
SLAVE ADDRESS
1
To generate this transfer:
Setting CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers with 10-
bit addressing is similar to transfers with 7-bit addresses, except that bits 10:7 of CMDR.ADR
must be set appropriately.
In
driven by the master, the white boxes are driven by the slave.
To perform a master transmitter transfer,
When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be
controlled. CMDR.REPSAME must be written to one when the address phase of the transfer
should consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The I²C
standard specifies that such addressing is required when addressing a slave for reads using
10-bit addressing.
To perform a master receiver transfer,
1
TWI_RHR
1st 7 bits
1. Program CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1.
2. Program NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0.
3. Wait until SR.RXRDY==1, then read first data byte received from RHR.
4. Wait until SR.RXRDY==1, then read second data byte received from RHR.
5. Wait until SR.TXRDY==1, then write first data byte to transfer to THR.
6. Wait until SR.TXRDY==1, then write second data byte to transfer to THR.
1. Program CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and
A
Read
Figure 21-14 on page 479
1
the desired address and NBYTES value.
0
DATA0
X
X
RW A1
0
DATA0
A
DATA1
SLAVE ADDRESS
2nd byte
and
DATA3
A
Figure 21-15 on page
Sr
DADR
A2
1
DATA
W
AT32UC3L016/32/64
A
A
480, the grey boxes represent signals
DATA2
DATA2
DATA
A
AA
P
DATA3
DATA3
NA
P
479
2
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