ATMEGA645P-MUR Atmel, ATMEGA645P-MUR Datasheet - Page 245

• Manufacturer Part Number: ATMEGA645P-MUR
• Description: MCU AVR 64KB FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645P-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.5.2
24.5.3
8285B–AVR–03/11
Scanning the RESET Pin
Scanning the Clock Pins
ATmega165A/165PA/325A/325PA/3250A/3250PA/6
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel programming. An observe-only cell as shown in
page 245
Figure 24-5. Observe-only Cell
The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-
tor, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and
Ceramic Resonator.
Figure 24-6 on page 245
scan chain. The Enable signal is supported with a general Boundary-scan cell, while the Oscilla-
tor/clock output is attached to an observe-only cell. In addition to the main clock, the timer
Oscillator is scanned in the same way. The output from the internal RC Oscillator is not scanned,
as this Oscillator does not have external connections.
Figure 24-6. Boundary-scan Cells for Oscillators and Clock Options
From Digital Logic
is inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.
Previous
From
Cell
From System Pin
ShiftDR
0
1
ClockDR
shows how each Oscillator with external connection is supported in the
D
UpdateDR
Q
Next
Cell
To
Previous
D
G
From
Cell
Q
ShiftDR
EXTEST
0
1
0
1
XTAL1/TOSC1
ClockDR
ENABLE
Oscillator
D
FF1
XTAL2/TOSC2
Q
OUTPUT
Next
Cell
To
Previous
From
To System Logic
Cell
ShiftDR
0
1
ClockDR
D
FF1
Q
Next
Cell
To
Figure 24-5 on
To System Logic
245