AT90USB646-MUR Atmel, AT90USB646-MUR Datasheet - Page 264
![MCU AVR 64K FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90USB646-MUR
Manufacturer Part Number
AT90USB646-MUR
Description
MCU AVR 64K FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB646-MU.pdf
(461 pages)
Specifications of AT90USB646-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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AT90USB64/128
• 3 – SRPSEL: SRP Selection Bit
Set to choose VBUS pulsing as SRP method.
Clear to choose data line pulsing as SRP method.
• 2 – VBUSHWC: VBus Hardware Control Bit
Set to disable the hardware control over the UVCON pin.
Clear to enable the hardware control over the UVCON pin.
See for more details
• 1 – VBUSREQ: VBUS Request Bit
Set to assert the UVCON pin in order to enable the VBUS power supply generation. This bit
shall be used when the controller is in the Host mode.
Cleared by hardware when VBUSRQC is set.
• 0 – VBUSRQC: VBUS Request Clear Bit
Set to deassert the UVCON pin in order to enable the VBUS power supply generation. This bit
shall be used when the controller is in the Host mode.
Cleared by hardware immediately after the set.
• 7 – Reserved
This bit is reserved and always set.
• 6-5 – PAGE: Timer page access Bit
Set/clear to access a special timer register. See Section 21.9, page 259 for more details.
• 4-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 1-0 – VALUE: Value Bit
Set to initialize the new value of the timer. See Section 21.9, page 259 for more details.
• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 – STOE: Suspend Time-out Error Interrupt Enable Bit
Set to enable the STOI interrupt. Clear to disable the STOI interrupt.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R
7
0
-
R
7
1
-
R
6
0
-
R/W
6
0
PAGE
STOE
R/W
5
0
R/W
0
5
HNPERRE
R/W
4
0
R
4
0
-
ROLEEXE
R/W
R
3
0
3
0
-
BCERRE
R/W
2
0
R/W
-
2
0
R/W
VBERRE
1
0
R/W
VALUE
1
0
R/W
0
0
SRPE
R/W
0
0
OTGTCON
7593K–AVR–11/09
OTGIEN
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