AT90USB646-MUR Atmel, AT90USB646-MUR Datasheet - Page 95

• Manufacturer Part Number: AT90USB646-MUR
• Description: MCU AVR 64K FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB646-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.0.2
11.0.3
7593K–AVR–11/09
External Interrupt Control Register B – EICRB
External Interrupt Mask Register – EIMSK
Table 11-1.
Note:
Table 11-2.
• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
rupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL
divider is enabled. If low level interrupt is selected, the low level must be held until the comple-
tion of the currently executing instruction to generate an interrupt. If enabled, a level triggered
interrupt will generate an interrupt request as long as the pin is held low.
Table 11-3.
Note:
Bit
Read/Write
Initial Value
Bit
Symbol
ISCn1
ISCn1
t
0
0
1
1
0
0
1
1
INT
1. n = 3, 2, 1or 0.
1. n = 7, 6, 5 or 4.
ISCn0
ISCn0
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Parameter
Minimum pulse width for
asynchronous external interrupt
0
1
0
1
0
1
0
1
7
ISC71
R/W
0
7
Asynchronous External Interrupt Characteristics
Interrupt Sense Control
Interrupt Sense Control
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request
The falling edge between two samples of INTn generates an interrupt
request.
The rising edge between two samples of INTn generates an interrupt
request.
Description
The low level of INTn generates an interrupt request.
Any edge of INTn generates asynchronously an interrupt request.
The falling edge of INTn generates asynchronously an interrupt request.
The rising edge of INTn generates asynchronously an interrupt request.
6
ISC70
R/W
0
6
5
ISC61
R/W
0
5
4
ISC60
R/W
0
4
(1)
Table
(1)
11-3. The value on the INT7:4 pins are sampled
3
ISC51
0
3
R/W
Condition
2
ISC50
R/W
0
2
Min
1
ISC41
R/W
0
1
AT90USB64/128
Typ
50
0
ISC40
R/W
0
0
Max
EICRB
Units
ns
95