PIC18F4480-E/P Microchip Technology, PIC18F4480-E/P Datasheet - Page 109
![IC PIC MCU FLASH 8KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4480-E/P
Manufacturer Part Number
PIC18F4480-E/P
Description
IC PIC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18F4480-IPT.pdf
(8 pages)
5.PIC18F4480-IPT.pdf
(6 pages)
6.PIC18F4480-IPT.pdf
(6 pages)
Specifications of PIC18F4480-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, MSSP, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4480-E/P
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC18F4480-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18F4480-IPT PDF datasheet #4
- PIC18F4480-IPT PDF datasheet #5
- PIC18F4480-IPT PDF datasheet #6
- Current page: 109 of 490
- Download datasheet (9Mb)
EXAMPLE 7-3:
7.5.2
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
7.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 7-2:
© 2009 Microchip Technology Inc.
TBLPTRU
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1:
PROGRAM_MEMORY
Name
Required
Sequence
2:
3:
These bits are available in PIC18F4X80 devices only.
These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices.
This bit is available only in Test mode and Serial Programming mode.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Pointer High Byte (TBLPTR<7:0>)
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIP
OSCFIF
OSCFIE
EEPGD
Bit 7
—
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DECFSZ
BRA
BSF
BCF
CMIP
CMIF
CMIE
CFGS
Bit 6
—
(2)
(2)
(2)
EECON1,EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
COUNTER1
WRITE_BUFFER_BACK
INTCON, GIE
EECON1, WREN
bit21
Bit 5
—
—
—
—
(3)
PIC18F2480/2580/4480/4580
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
FREE
INTE
EEIP
EEIF
EEIE
Bit 4
WRERR
BCLIP
BCLIF
BCLIE
RBIE
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
Bit 3
7.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 25.0 “Special Features of the
CPU” for more detail.
7.6
See Section 25.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TMR0IF
HLVDIP
HLVDIE
HLVDIF
WREN
Bit 2
Flash Program Operation During
Code Protection
PROTECTION AGAINST SPURIOUS
WRITES
TMR3IP
TMR3IF
TMR3IE
Bit 1
INTF
WR
ECCP1IP
ECCP1IF
ECCP1IE
RBIF
Bit 0
RD
DS39637D-page 109
(1)
(1)
(1)
on Page:
Values
Reset
55
55
55
55
55
57
57
57
58
58
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