PIC18F4480-E/P Microchip Technology, PIC18F4480-E/P Datasheet - Page 202
![IC PIC MCU FLASH 8KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4480-E/P
Manufacturer Part Number
PIC18F4480-E/P
Description
IC PIC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18F4480-IPT.pdf
(8 pages)
5.PIC18F4480-IPT.pdf
(6 pages)
6.PIC18F4480-IPT.pdf
(6 pages)
Specifications of PIC18F4480-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, MSSP, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4480-E/P
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC18F4480-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18F4480-IPT PDF datasheet #4
- PIC18F4480-IPT PDF datasheet #5
- PIC18F4480-IPT PDF datasheet #6
- Current page: 202 of 490
- Download datasheet (9Mb)
PIC18F2480/2580/4480/4580
REGISTER 18-4:
DS39637D-page 202
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
WCOL
R/W-0
2:
When enabled, the SDA and SCL pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: SCK Release Control bit
In Slave mode:
1 = Releases clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
SSPM<3:0>: Master Synchronous Serial Port Mode Select bits
1111 = I
1110 = I
1011 = I
1000 = I
0111 = I
0110 = I
SSPOV
R/W-0
transmission to be started (must be cleared in software)
software)
software)
SSPCON1: MSSP CONTROL REGISTER 1 (I
2
2
2
2
2
2
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Firmware Controlled Master mode (slave Idle)
C Master mode, clock = F
C Slave mode, 10-bit address
C Slave mode, 7-bit address
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
(1)
R/W-0
CKP
OSC
/(4 * (SSPADD + 1))
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
(1)
(2)
2
C™ MODE)
SSPM2
R/W-0
(2)
2
C conditions were not valid for a
(2)
© 2009 Microchip Technology Inc.
x = Bit is unknown
SSPM1
R/W-0
(2)
SSPM0
R/W-0
bit 0
(2)
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