PIC18F4480-E/P Microchip Technology, PIC18F4480-E/P Datasheet - Page 35
![IC PIC MCU FLASH 8KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4480-E/P
Manufacturer Part Number
PIC18F4480-E/P
Description
IC PIC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18F4480-IPT.pdf
(8 pages)
5.PIC18F4480-IPT.pdf
(6 pages)
6.PIC18F4480-IPT.pdf
(6 pages)
Specifications of PIC18F4480-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, MSSP, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4480-E/P
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC18F4480-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18F4480-IPT PDF datasheet #4
- PIC18F4480-IPT PDF datasheet #5
- PIC18F4480-IPT PDF datasheet #6
- Current page: 35 of 490
- Download datasheet (9Mb)
3.7.1
The OSCCON register (Register 3-2) controls several
aspects of the device clock’s operation, both in
full-power operation and in power-managed modes.
The System Clock Select bits, SCS<1:0>, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC<3:0> Configura-
tion bits), the secondary clock (Timer1 oscillator) and
the internal oscillator block. The clock source changes
immediately after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.
The
IRCF<2:0>, select the frequency output of the internal
oscillator block to drive the device clock. The choices
are the INTRC source, the INTOSC source (8 MHz) or
one of the frequencies derived from the INTOSC post-
scaler (31 kHz to 4 MHz). If the internal oscillator block
is supplying the device clock, changing the states of
these bits will have an immediate change on the inter-
nal oscillator’s output. On device Resets, the default
output frequency of the internal oscillator block is set at
1 MHz.
When an output frequency of 31 kHz is selected
(IRCF<2:0> = 000), users may choose which internal
oscillator acts as the source. This is done with the
INTSRC bit in the OSCTUNE register (OSCTUNE<7>).
Setting this bit selects INTOSC as a 31.25 kHz clock
source by enabling the divide-by-256 output of the
INTOSC postscaler. Clearing INTSRC selects INTRC
(nominally 31 kHz) as the clock source.
This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the device clock. The
OSTS bit indicates that the Oscillator Start-up Timer
(OST) has timed out and the primary clock is providing
the device clock in primary clock modes. The IOFS bit
indicates when the internal oscillator block has stabi-
lized and is providing the device clock in RC Clock
modes. The T1RUN bit (T1CON<6>) indicates when
the Timer1 oscillator is providing the device clock in
secondary clock modes. In power-managed modes,
only one of these three bits will be set at any time. If
none of these bits are set, the INTRC is providing the
clock or the internal oscillator block has just started and
is not yet stable.
© 2009 Microchip Technology Inc.
Internal
OSCILLATOR CONTROL REGISTER
Oscillator
Frequency
Select
PIC18F2480/2580/4480/4580
bits,
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-Managed Modes”.
3.7.2
PIC18F2480/2580/4480/4580 devices contain circuitry
to prevent clock “glitches” when switching between
clock sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
2: It is recommended that the Timer1
OSCILLATOR TRANSITIONS
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEP instruction will be ignored.
oscillator be operating and stable before
executing the SLEEP instruction, or a very
long delay may occur while the Timer1
oscillator starts.
DS39637D-page 35
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