ATMEGA649P-MUR Atmel, ATMEGA649P-MUR Datasheet - Page 204

• Manufacturer Part Number: ATMEGA649P-MUR
• Description: AVR, 64KB FLASH, 2KB EE, 4KB SRA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA649P-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20. USI – Universal Serial Interface
20.1
20.2
8284A–AVR–10/10
Features
Overview
•
•
•
•
•
•
The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown in
ment of I/O pins, refer to
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the
Figure 20-1. Universal Serial Interface, Block Diagram
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and
outgoing data. The register has no buffering so the data must be read as quickly as possible to
ensure that no data is lost. The most significant bit is connected to one of two output pins
depending of the wire mode configuration. A transparent latch is inserted between the Serial
Register Output and output pin, which delays the change of data output to the opposite clock
edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin
independent of the configuration.
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wake up from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
USIDR
USICR
USISR
”Register Description” on page
2
4-bit Counter
”Pin Configurations” on page
3
2
1
0
3
2
1
0
D Q
LE
[1]
Figure 20-1 on page 204
TIM0 COMP
0
1
212.
Two-wire Clock
Control Unit
2. CPU accessible I/O Registers,
CLOCK
HOLD
DO
DI/SDA
USCK/SCL
For the actual place-
(Output only)
(Input/Open Drain)
(Input/Open Drain)
204