PIC18F452-I/PG Microchip Technology, PIC18F452-I/PG Datasheet - Page 162
![IC MCU FLASH 16KX16 W/AD 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F452-I/PG
Manufacturer Part Number
PIC18F452-I/PG
Description
IC MCU FLASH 16KX16 W/AD 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18F452-I/PG
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
ACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- Current page: 162 of 332
- Download datasheet (6Mb)
PIC18FXX2
15.4.17.1
During a START condition, a bus collision occurs if:
a)
b)
During a START condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the START condition is aborted,
• the BCLIF flag is set, and
• the MSSP module is reset to its IDLE state
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
FIGURE 15-26:
DS39564C-page 160
(Figure 15-26).
SDA
SCL
SEN
BCLIF
S
SSPIF
SDA or SCL are sampled low at the beginning of
the START condition (Figure 15-26).
SCL is sampled low before SDA is asserted low
(Figure 15-27).
Bus Collision During a START
Condition
BUS COLLISION DURING START CONDITION (SDA ONLY)
condition if SDA = 1, SCL=1
Set SEN, enable START
SDA sampled low before
START condition.
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
Set BCLIF.
SSPIF and BCLIF are
cleared in software.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 15-28). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pins
are sampled as '0', a bus collision does not occur. At
the end of the BRG count, the SCL pin is asserted low.
Note:
SEN cleared automatically because of bus collision.
SSP module reset into IDLE state.
The reason that bus collision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time.
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START or STOP conditions.
SSPIF and BCLIF are
cleared in software.
© 2006 Microchip Technology Inc.
Therefore, one
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