PIC18F452-I/PG Microchip Technology, PIC18F452-I/PG Datasheet - Page 168
![IC MCU FLASH 16KX16 W/AD 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F452-I/PG
Manufacturer Part Number
PIC18F452-I/PG
Description
IC MCU FLASH 16KX16 W/AD 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18F452-I/PG
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
ACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- Current page: 168 of 332
- Download datasheet (6Mb)
PIC18FXX2
REGISTER 16-1:
DS39564C-page 166
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note:
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
TX9D: 9th bit of Transmit Data
Can be Address/Data bit or a parity bit.
Legend:
R = Readable bit
- n = Value at POR
R/W-0
CSRC
SREN/CREN overrides TXEN in SYNC mode.
R/W-0
TX9
R/W-0
TXEN
W = Writable bit
’1’ = Bit is set
R/W-0
SYNC
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U-0
—
R/W-0
BRGH
© 2006 Microchip Technology Inc.
x = Bit is unknown
TRMT
R-1
R/W-0
TX9D
bit 0
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