PIC18F86J65-I/PT Microchip Technology, PIC18F86J65-I/PT Datasheet - Page 139

• Manufacturer Part Number: PIC18F86J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 55
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.0
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
• LAT register (Output Latch register)
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
FIGURE 10-1:
© 2009 Microchip Technology Inc.
device)
RD LAT
Data
Bus
WR LAT
or PORT
WR TRIS
RD TRIS
RD PORT
I/O PORTS
TRIS Latch
Data Latch
D
D
CK
CK
GENERIC I/O PORT
OPERATION
Q
Q
Q
EN
EN
D
Input
Buffer
I/O pin
PIC18F97J60 FAMILY
10.1
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than V
10.1.1
The output pin drive strengths vary for groups of pins
intended to meet the needs for a variety of applications.
PORTB and PORTC are designed to drive higher
loads, such as LEDs. The external memory interface
ports (PORTD, PORTE and PORTJ) are designed to
drive medium loads. All other ports are designed for
small loads, typically indication only. Table 10-1 sum-
marizes the output capabilities. Refer to Section 27.0
“Electrical Characteristics” for more details.
TABLE 10-1:
PORTA
PORTF
PORTG
PORTH
PORTD
PORTE
PORTJ
PORTB
PORTC
Note 1:
Port
2:
3:
(3)
(1)
(2)
(3)
(2)
(2)
I/O Port Pin Capabilities
The exceptions are RA0:RA1, which are
capable of directly driving LEDs.
Partially implemented on 64-pin and
80-pin devices; fully implemented on
100-pin devices.
Unimplemented on 64-pin devices.
PIN OUTPUT DRIVE
Minimum Intended for indication.
Medium
Drive
High
OUTPUT DRIVE LEVELS
Sufficient drive levels for
external memory interfacing,
as well as indication.
Suitable for direct LED drive
levels.
Description
DS39762E-page 139
DD
input levels.