PIC18F86J65-I/PT Microchip Technology, PIC18F86J65-I/PT Datasheet - Page 152

• Manufacturer Part Number: PIC18F86J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 55
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
TABLE 10-11:
DS39762E-page 152
RE0/AD8/RD/
P2D
RE1/AD9/WR/
P2C
RE2/AD10/CS/
P2B
RE3/AD11/
P3C
RE4/AD12/
P3B
Legend:
Note 1:
Pin Name
2:
3:
4:
5:
6:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
EMB functions implemented on 100-pin devices only.
External memory interface I/O takes priority over all other digital and PSP I/O.
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin and 100-pin devices).
Unimplemented on 64-pin devices.
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (80-pin and 100-pin devices in
Microcontroller mode).
Unimplemented on 64-pin and 80-pin devices.
Function
AD10
AD11
AD12
AD8
AD9
P3C
P3B
PORTE FUNCTIONS
WR
RD
CS
RE0
P2D
RE1
P2C
RE2
RE3
RE4
P2B
(6)
(6)
(6)
(1)
(1)
(3)
(3)
(1)
(1)
(1)
Setting
TRIS
0
1
x
x
1
0
0
1
x
x
1
0
0
1
x
x
1
0
0
1
x
x
0
0
1
x
x
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
I/O
ST
ST
ST
ST
ST
LATE<0> data output.
PORTE<0> data input; weak pull-up when REPU bit is set.
External memory interface, address/data bit 8 output.
External memory interface, data bit 8 input.
Parallel Slave Port read enable control input.
ECCP2 Enhanced PWM output, channel D; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<1> data output.
PORTE<1> data input; weak pull-up when REPU bit is set.
External memory interface, address/data bit 9 output.
External memory interface, data bit 9 input.
Parallel Slave Port write enable control input.
ECCP2 Enhanced PWM output, channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<2> data output.
PORTE<2> data input; weak pull-up when REPU bit is set.
External memory interface, address/data bit 10 output.
External memory interface, data bit 10 input.
Parallel Slave Port chip select control input.
ECCP2 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<3> data output.
PORTE<3> data input; weak pull-up when REPU bit is set.
External memory interface, address/data bit 11 output.
External memory interface, data bit 11 input.
ECCP3 Enhanced PWM output, channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<4> data output.
PORTE<4> data input; weak pull-up when REPU bit is set.
External memory interface, address/data bit 12 output.
External memory interface, data bit 12 input.
ECCP3 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Description
© 2009 Microchip Technology Inc.
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
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