PIC18F86J65-I/PT Microchip Technology, PIC18F86J65-I/PT Datasheet - Page 211

• Manufacturer Part Number: PIC18F86J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 55
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.1.4
To complete the Ethernet interface, the Ethernet
module requires several standard components to be
installed externally. These components should be
connected as shown in Figure 18-2.
The internal analog circuitry in the PHY module requires
that an external resistor (2.26 kΩ) be attached from
RBIAS to ground. The resistor influences the TPOUT+/-
signal amplitude. It should be placed as close as possible
to the chip with no immediately adjacent signal traces to
prevent noise capacitively coupling into the pin and
affecting the transmit behavior. It is recommended that
the resistor be a surface mount type.
On the TPIN+/TPIN- and TPOUT+/TPOUT- pins,
1:1 center-tapped pulse transformers rated for Ethernet
operations (10/100 or 10/100/1000) are required. When
the Ethernet module is enabled, current is continually
sunk through both TPOUT pins. When the PHY is
actively transmitting, a differential voltage is created on
the Ethernet cable by varying the relative current sunk
by TPOUT+ compared to TPOUT-.
A common-mode choke on the PHY side of the interface
(i.e., between the microcontrollers’s TPOUT pins and
the Ethernet transformer) is not recommend. If a com-
FIGURE 18-2:
© 2009 Microchip Technology Inc.
Note 1:
2:
3:
4:
25 MHz
C2
C1
MAGNETICS, TERMINATION AND
OTHER EXTERNAL COMPONENTS
(4)
Ferrite Bead should be rated for at least 80 mA.
These components are installed for EMI reduction purposes. Power Over Ethernet applications may require their removal.
Recommended insertion point for Common-Mode Chokes (CMCs) if required for EMI reduction.
See Section 2.3 “Crystal Oscillator/Ceramic Resonators (HS Modes)” for recommended values.
(4)
OSC2
OSC1
EXTERNAL COMPONENTS REQUIRED FOR ETHERNET OPERATION
LEDA
PIC18FXXJ6X
LEDB
TPOUT+
TPOUT-
RBIAS
TPIN+
TPIN-
49.9Ω, 1%
49.9Ω, 1%
49.9Ω, 1%
49.9Ω, 1%
2.26 kΩ, 1%
PIC18F97J60 FAMILY
mon-mode choke is used to reduce EMI emissions, it
should be placed between the Ethernet transformer and
pins 1 and 2 of the RJ-45 connector. Many Ethernet
transformer modules include common-mode chokes
inside the same device package. The transformers
should have at least the isolation rating specified in
Table 27-28 to protect against static voltages and meet
IEEE 802.3 isolation requirements (see Section 27.5
“Ethernet Specifications and Requirements” for
specific transformer requirements). Both transmit and
receive interfaces additionally require two resistors and
a capacitor to properly terminate the transmission line,
minimizing signal reflections.
All power supply pins must be externally connected to
the same power source. Similarly, all ground refer-
ences must be externally connected to the same
ground node. Each V
a 0.1 μF ceramic bypass capacitor placed as close to
the pins as possible.
Since relatively high currents are necessary to operate
the twisted-pair interface, all wires should be kept as
short as possible. Reasonable wire widths should be
used on power wires to reduce resistive loss. If the
differential data lines cannot be kept short, they should
be routed in such a way as to have a 100Ω characteristic
impedance.
3.3V
Ferrite
Bead
0.1 μF
0.1 μF
(1,2)
(2)
1:1 CT
1:1 CT
DD
and V
SS
CMC
CMC
pin pair should have
1 nF, 2 kV
(3)
(3)
DS39762E-page 211
(3)
RJ-45
1
2
3
4
5
6
7
8
1