PIC18F252-E/SO Microchip Technology, PIC18F252-E/SO Datasheet - Page 33

• Manufacturer Part Number: PIC18F252-E/SO
• Description: IC MCU CMOS 40MHZ 16K FLSH28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F252-E/SO

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 3-3:
© 2006 Microchip Technology Inc.
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
TRISE
TRISD
TRISC
TRISB
TRISA
LATE
LATD
LATC
LATB
LATA
PORTE
PORTD
PORTC
PORTB
PORTA
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
Register
(5,6)
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.
(5,6)
(5,6)
Shaded cells indicate conditions do not apply for the designated device.
vector (0008h or 0018h).
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
Oscillator modes, they are disabled and read ’0’.
242
242
242
242
242
242
242
242
242
242
242
242
242
242
242
242
242
242
242
242
242
242
242
242
Applicable Devices
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
442
442
442
442
442
442
442
442
442
442
442
442
442
442
442
442
442
442
442
442
442
442
442
442
252
252
252
252
252
252
252
252
252
252
252
252
252
252
252
252
252
252
252
252
252
252
252
252
452
452
452
452
452
452
452
452
452
452
452
452
452
452
452
452
452
452
452
452
452
452
452
452
Brown-out Reset
Power-on Reset,
---1 1111
---0 0000
---0 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
0000 -111
1111 1111
1111 1111
1111 1111
-111 1111
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
---- -000
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x0x 0000
(5)
(5)
(5)
RESET Instruction
MCLR Resets
Stack Resets
---1 1111
---0 0000
---0 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
0000 -111
1111 1111
1111 1111
1111 1111
-111 1111
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- -000
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u0u 0000
WDT Reset
(5)
(5)
(5)
PIC18FXX2
Wake-up via WDT
---u uuuu
---u uuuu
---u uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
-uuu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
or Interrupt
DS39564C-page 31
(1)
(1)
(1)
(5)
(5)
(5)