PIC18F252-E/SO Microchip Technology, PIC18F252-E/SO Datasheet - Page 93

• Manufacturer Part Number: PIC18F252-E/SO
• Description: IC MCU CMOS 40MHZ 16K FLSH28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F252-E/SO

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 9-5:
FIGURE 9-6:
© 2006 Microchip Technology Inc.
Note 1:
Note 1:
2:
2:
3:
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
CCP Output
CCP2 Input
I/O pin has diode protection to V
To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).
The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (=’0’) in the configuration register.
RD PORTB
Enable
CCP Output
WR LATB or
WR PORTB
WR TRISB
RBPU
Data Bus
BLOCK DIAGRAM OF RB2:RB0 PINS
BLOCK DIAGRAM OF RB3 PIN
(3)
(2)
CCP2MX
(3)
(3)
Data Bus
WR TRIS
WR Port
RB0/INT
RBPU
(2)
Schmitt Trigger
Buffer
RD TRISB
RD PORTB
RD LATB
TRIS Latch
Data Latch
D
D
CK
CK
DD
DD
and V
Q
Q
and V
RD TRIS
RD Port
TRIS Latch
Data Latch
CCP2MX = 0
D
D
CK
CK
SS
SS
.
Schmitt Trigger
Buffer
.
Q
Q
Q
1
0
EN
D
Q
EN
TTL
Input
Buffer
D
V
P
RD Port
DD
Weak
Pull-up
V
I/O pin
V
N
P
SS
DD
(1)
TTL
Input
Buffer
V
P
DD
Weak
Pull-up
PIC18FXX2
I/O pin
(1)
DS39564C-page 91