PIC18F4455-I/P Microchip Technology, PIC18F4455-I/P Datasheet - Page 13

• Manufacturer Part Number: PIC18F4455-I/P
• Description: IC PIC MCU FLASH 12KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4455-I/P

• Program Memory Type: FLASH
• Program Memory Size: 24KB (12K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26. Module: MSSP
27. Module: MSSP
© 2009 Microchip Technology Inc.
With MSSP in SPI Master mode, F
Timer2/2 clock rate and CKE = 0, a write collision
may occur if SSPBUF is loaded immediately after
the transfer is complete. A delay may be required
after the MSSP Interrupt Flag bit (SSPIF) is set or
the Buffer Full bit (BF) is set – before writing
SSPBUF. If the delay is insufficiently short, a write
collision may occur as indicated by the WCOL bit
being set.
Work around
Add a software delay of one SCK period after
detecting the completed transfer and prior to
updating the SSPBUF contents.
Affected Silicon Revisions
In an I
unaddressed slave may respond to bus activity
when data on the bus matches its address. The
first occurrence will set the BF bit. The second
occurrence will set the BF and SSPOV bits. In both
situations, the SSPIF bit is not set and an interrupt
will not occur. The device will vector to the Interrupt
Service Routine only if the interrupt is enabled and
an address match occurs.
Work around
The I
I
Affected Silicon Revisions
2
C event to maintain normal operation.
A3
A3
X
X
2
C slave must clear the SSPOV bit after each
2
C system with multiple slave nodes, an
B4
B4
X
B5
B5
X
B6
B6
X
OSC
PIC18F2455/2550/4455/4550
/64 or
B7
B7
X
28. Module: EUSART
29. Module: A/D
30. Module: Resets (BOR)
The EUSART auto-baud feature may periodically
measure the incoming baud rate incorrectly. The
rate of incorrect baud-rate measurements will
depend on the frequency of the incoming
synchronization byte and the system clock
frequency.
Work around
None.
Affected Silicon Revisions
When the A/D clock source is selected as 2 T
or RC (when ADCS<2:0> = 000 or x11), in
extremely rare cases, the E
Error) and E
exceed the data sheet specification at codes 511
and 512 only.
Work around
Select a different A/D clock source (4 T
8 T
selecting the 2 T
Affected Silicon Revisions
If either the HLVD or USB modules are enabled,
clearing the SBOREN bit (RCON<6>) when the soft-
ware
(BOREN<1:0> = 01) may cause a Brown-out Reset
(BOR) event.
Work around
Before clearing the SBOREN bit, temporarily
disable the HLVD and USB modules.
Affected Silicon Revisions
OSC
A3
A3
A3
X
X
X
, 16 T
controlled
OSC
DL
B4
B4
B4
X
OSC
(Differential Linearity Error) may
, 32 T
BOR
or RC modes.
B5
OSC
B5
B5
X
, 64 T
feature
IL
(Integral Linearity
DS80478A-page 13
B6
B6
B6
OSC
) and avoid
is
enabled
B7
B7
B7
OSC
OSC
,