PIC18F4455-I/P Microchip Technology, PIC18F4455-I/P Datasheet - Page 3

• Manufacturer Part Number: PIC18F4455-I/P
• Description: IC PIC MCU FLASH 12KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4455-I/P

• Program Memory Type: FLASH
• Program Memory Size: 24KB (12K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 2:
© 2009 Microchip Technology Inc.
BOR
MSSP
MSSP
Timer1/3
BOR
BOR
EUSART
MSSP
MSSP
MSSP
MSSP
EUSART
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
HLVD or USB
I
Eight-Bit
Async
Threshold
Synch
Master
I
I
SPI slave
Threshold
SPI Slave
SPI modes
Interrupts
2
2
2
C mode
C Slave
C Master
Feature
SILICON ISSUE SUMMARY (CONTINUED)
Number
Item
30.
31.
33.
34.
35.
36.
39.
40.
41.
32.
37.
38.
Clearing SBOREN can cause BOR
I
SPI slave not meeting timing parameter 70
Need delay between consecutive writes
Certain conditions move BOR threshold
Table reads can move BOR threshold
Synchronous master mode, DT data changes
SPI Slave needs a series resistor
SPI modes, incoming data not received if BF set
With I
promptly
In I
slave clock stretch
If interrupts are enabled, 2 T
after re-enabling the module
2
C baud rate not meeting formula
2
C Master mode, narrow clock width upon
2
C slave reception, need to read data
PIC18F2455/2550/4455/4550
Issue Summary
CY
delay needed
A3
X
X
X
Affected Revisions
B4
X
X
X
X
X
X
X
X
DS80478A-page 3
B5
X
X
X
X
X
X
X
B6
X
X
X
X
X
X
X
(1)
B7
X
X
X
X
X
X