PIC18F442-E/PT Microchip Technology, PIC18F442-E/PT Datasheet - Page 154
![IC MCU CMOS 40MHZ 8K FLSH 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F442-E/PT
Manufacturer Part Number
PIC18F442-E/PT
Description
IC MCU CMOS 40MHZ 8K FLSH 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18F442-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F442-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- Current page: 154 of 332
- Download datasheet (6Mb)
PIC18FXX2
15.4.7.1
Clock arbitration occurs when the master, during any
receive, transmit or Repeated START/STOP condition,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
FIGURE 15-18:
DS39564C-page 152
Clock Arbitration
SDA
SCL
BRG
Value
BRG
Reload
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
03h
DX
SCL de-asserted but slave holds
SCL low (clock arbitration)
02h
SCL is sampled high, reload takes
place and BRG starts its count.
01h
BRG decrements on
Q2 and Q4 cycles
00h (hold off)
DX-1
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 15-18).
SCL allowed to transition high
03h
© 2006 Microchip Technology Inc.
02h
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