PIC18F442-E/PT Microchip Technology, PIC18F442-E/PT Datasheet - Page 177
![IC MCU CMOS 40MHZ 8K FLSH 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F442-E/PT
Manufacturer Part Number
PIC18F442-E/PT
Description
IC MCU CMOS 40MHZ 8K FLSH 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18F442-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F442-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- Current page: 177 of 332
- Download datasheet (6Mb)
FIGURE 16-5:
TABLE 16-7:
© 2006 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented locations read as '0'.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits
Name
Note:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Shaded cells are not used for Asynchronous Reception.
clear.
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing
the OERR (overrun) bit to be set.
USART Receive Register
Baud Rate Generator Register
GIE/GIEH
PSPIE
PSPIP
PSPIF
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
START
ASYNCHRONOUS RECEPTION
bit
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit0
TMR0IE INT0IE
bit1
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
CREN ADDEN FERR
SYNC
TXIE
TXIP
Bit 4
TXIF
bit7/8
STOP
bit
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
RBIE
Bit 3
—
Word 1
RCREG
START
bit
TMR0IF INT0IF
BRGH
Bit 2
bit0
OERR
TRMT
Bit 1
bit7/8 STOP
Word 2
RCREG
RX9D
TX9D
RBIF
Bit 0
bit
START
bit
PIC18FXX2
0000 000x
0000 -00x
0000 0000
0000 -010
0000 0000
POR, BOR
Value on
bit7/8
DS39564C-page 175
STOP
0000 000u
0000 0000
0000 0000
0000 0000
0000 -00x
0000 0000
0000 -010
0000 0000
Value on
All Other
bit
RESETS
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