DSPIC30F5015-30I/PT Microchip Technology, DSPIC30F5015-30I/PT Datasheet - Page 225

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 66KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F501530IPT

Timing Requirements
Timing Specifications
Traps .................................................................................. 43
© 2007 Microchip Technology Inc.
SPI Slave Mode (CKE = 0) ...................................... 200
SPI Slave Mode (CKE = 1) ...................................... 201
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR
TimerQ (QEI Module) External Clock ...................... 192
Timer1, 2, 3, 4, 5 External Clock .............................. 190
10-bit High-Speed A/D Conversion (CHPS = 01,
10-bit High-Speed A/D Conversion (CHPS = 01,
A/D Conversion ........................................................ 212
Band Gap Start-up Time .......................................... 189
CAN Module I/O ....................................................... 207
CLKOUT and I/O ...................................................... 187
External Clock .......................................................... 183
Input Capture ........................................................... 193
I
I
Motor Control PWM Module ..................................... 195
Output Compare ...................................................... 193
QEI Module External Clock ...................................... 192
QEI Module Index Pulse .......................................... 197
Quadrature Decoder ................................................ 196
Reset, Watchdog Timer, Oscillator Start-up Timer,
Simple OC/PWM Mode ............................................ 194
SPI Master Mode (CKE = 0) .................................... 198
SPI Master Mode (CKE = 1) .................................... 199
SPI Slave Mode (CKE = 0) ...................................... 200
SPI Slave Mode (CKE = 1) ...................................... 202
Timer1 External Clock .............................................. 190
Timer2 and Timer4 External Clock .......................... 191
Timer3 and Timer5 External Clock .......................... 191
PLL Clock ................................................................. 184
Hard and Soft ............................................................. 44
Sources ...................................................................... 43
Vectors ....................................................................... 44
2
2
C Bus Data (Master Mode) .................................... 204
C Bus Data (Slave Mode) ...................................... 206
Tied to V
Tied to V
Tied to V
SIMSAM = 0, ASAM = 0, SSRC = 000) ........... 210
SIMSAM = 0, ASAM = 1, SSRC = 111,
SAMC = 00001) ............................................... 211
Power-up Timer and Brown-out Reset ............ 189
DD
DD
DD
), Case 1 ........................................ 140
), Case 2 ........................................ 141
) ..................................................... 140
U
UART
Unit ID Locations ............................................................. 133
Universal Asynchronous Receiver Transmitter
W
Wake-up from Sleep ........................................................ 133
Wake-up from Sleep and Idle ............................................ 45
Watchdog Timer (WDT) ........................................... 133, 144
WWW Address ................................................................ 225
WWW, On-Line Support ...................................................... 5
Z
10-Bit High-Speed Analog-to-Digital (A/D) Converter
16-bit Up/Down Position Counter Mode ............................ 88
8-Output PWM
dsPIC30F5015/5016
Address Detect Mode .............................................. 119
Auto-Baud Support .................................................. 120
Baud Rate Generator .............................................. 119
Disabling .................................................................. 117
Enabling ................................................................... 117
Loopback Mode ....................................................... 119
Module Overview ..................................................... 115
Operation During CPU Sleep and Idle Modes ......... 120
Receiving Data ........................................................ 118
Reception Error Handling ........................................ 118
Setting Up Data, Parity and Stop Bit Selections ...... 117
Transmitting Data .................................................... 117
UART1 Register Map .............................................. 121
Module (UART) ........................................................ 115
Enabling and Disabling ............................................ 144
Operation ................................................................. 144
Module ..................................................................... 149
Count Direction Status ............................................... 88
Error Checking ........................................................... 88
Register Map ........................................................... 102
In 8-bit or 9-bit Data Mode ............................... 118
Interrupt ........................................................... 118
Receive Buffer (UxRXB) .................................. 118
Framing Error (FERR Bit) ................................ 119
Idle Status ....................................................... 119
Parity Error (PERR Bit) .................................... 119
Receive Break ................................................. 119
Receive Buffer Overrun Error (OERR Bit) ....... 118
In 8-bit Data Mode ........................................... 117
In 9-bit Data Mode ........................................... 117
Interrupt ........................................................... 118
Transmit Buffer (UxTXB) ................................. 117
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