ATMEGA1280V-8AUR Atmel, ATMEGA1280V-8AUR Datasheet - Page 347

MCU AVR 128K FLASH 8MHZ 100TQFP

ATMEGA1280V-8AUR

Manufacturer Part Number
ATMEGA1280V-8AUR
Description
MCU AVR 128K FLASH 8MHZ 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA1280V-8AUR

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
86
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK503 - STARTER KIT AVR EXP MODULE 100P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA1280V-8AUR
Manufacturer:
Atmel
Quantity:
10 000
29.7.13
29.7.14
29.7.15
2549M–AVR–09/10
Reading the Signature Bytes
Reading the Calibration Byte
Parallel Programming Characteristics
Figure 29-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
The algorithm for reading the Signature bytes is as follows (refer to
page 341
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte (0x00 - 0x02).
3. Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA.
4. Set OE to “1”.
The algorithm for reading the Calibration byte is as follows (refer to
page 341
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4. Set OE to “1”.
Figure 29-7. Parallel Programming Timing, Including some General Timing Requirements
(DATA, XA0/1, BS1, BS2)
for details on Command and Address loading):
for details on Command and Address loading):
Data & Contol
RDY/BSY
Extended Fuse Byte
PAGEL
Fuse Low Byte
XTAL1
Fuse High Byte
WR
Lock Bits
t
t
BVPH
DVXH
ATmega640/1280/1281/2560/2561
BS2
BS2
t
t
XHXL
PHPL
0
1
0
1
t
t
t
t
XLDX
PLBX
XLWL
PLWL
t
BVWL
BS1
t
WLWH
WLRL
0
1
“Programming the Flash” on
“Programming the Flash” on
DATA
t
WLBX
t
WLRH
347

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