ATMEGA1280V-8AUR Atmel, ATMEGA1280V-8AUR Datasheet - Page 440

• Manufacturer Part Number: ATMEGA1280V-8AUR
• Description: MCU AVR 128K FLASH 8MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1280V-8AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK503 - STARTER KIT AVR EXP MODULE 100P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2549M–AVR–09/10
23 2-wire Serial Interface .......................................................................... 241
24 AC – Analog Comparator .................................................................... 271
25 ADC – Analog to Digital Converter ..................................................... 275
26 JTAG Interface and On-chip Debug System ..................................... 296
27 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 302
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
24.1
24.2
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
27.1
27.2
Features ........................................................................................................241
2-wire Serial Interface Bus Definition ............................................................241
Data Transfer and Frame Format ..................................................................242
Multi-master Bus Systems, Arbitration and Synchronization .........................245
Overview of the TWI Module .........................................................................246
Using the TWI ................................................................................................249
Transmission Modes .....................................................................................252
Multi-master Systems and Arbitration ............................................................265
Register Description ......................................................................................266
Analog Comparator Multiplexed Input ...........................................................271
Register Description ......................................................................................272
Features ........................................................................................................275
Operation .......................................................................................................276
Starting a Conversion ....................................................................................277
Prescaling and Conversion Timing ................................................................278
Changing Channel or Reference Selection ...................................................282
ADC Noise Canceler .....................................................................................283
ADC Conversion Result .................................................................................288
Register Description ......................................................................................289
Features ........................................................................................................296
Overview ........................................................................................................296
TAP - Test Access Port .................................................................................297
Using the Boundary-scan Chain ....................................................................299
Using the On-chip Debug System .................................................................299
On-chip Debug Specific JTAG Instructions ...................................................300
Using the JTAG Programming Capabilities ...................................................301
Bibliography ...................................................................................................301
On-chip Debug Related Register in I/O Memory ...........................................301
Features ........................................................................................................302
System Overview ...........................................................................................302
ATmega640/1280/1281/2560/2561
v