AT91SAM9G10-CU Atmel, AT91SAM9G10-CU Datasheet - Page 13
![IC MCU ARM9 SAMPLING 217CBGA](/photos/12/13/121366/217-lfbga_sml.jpg)
AT91SAM9G10-CU
Manufacturer Part Number
AT91SAM9G10-CU
Description
IC MCU ARM9 SAMPLING 217CBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G10-CU.pdf
(39 pages)
Specifications of AT91SAM9G10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
266MHz
Connectivity
EBI/EMI, I²C, IrDA, ISI, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Controller Family/series
AT91
No. Of I/o's
96
Ram Memory Size
16KB
Cpu Speed
266MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
EBI, SPI, TWI, USART
Maximum Clock Frequency
266 MHz
Number Of Programmable I/os
96
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9G10-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9G10-CU
Manufacturer:
Atmel
Quantity:
1 466
Part Number:
AT91SAM9G10-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
7. Processor and Architecture
7.1
6462AS–ATARM–03-Jun-09
ARM926EJ-S Processor
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
• Two Instruction Sets
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
• 16 Kbyte Data Cache, 16 Kbyte Instruction Cache
• Write Buffer
• Standard ARM v4 and v5 Memory Management Unit (MMU)
• Bus Interface Unit (BIU)
acceleration
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
– 16 embedded domains
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete AHB
– Separate Address and Data Buses for both the 32-bit instruction interface and the
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
each quarter of the page
system flexibility
32-bit data interface
(Words)
AT91SAM9G10
13