AT91SAM9G10-CU Atmel, AT91SAM9G10-CU Datasheet - Page 24

• Manufacturer Part Number: AT91SAM9G10-CU
• Description: IC MCU ARM9 SAMPLING 217CBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, I²C, IrDA, ISI, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Controller Family/series: AT91
• No. Of I/o's: 96
• Ram Memory Size: 16KB
• Cpu Speed: 266MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: EBI, SPI, TWI, USART
• Maximum Clock Frequency: 266 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9G10-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

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PIO Controllers
AT91SAM9G10
• Chip ID Registers
• ICE Access prevention
• Three PIO Controllers, each controlling up to 32 programmable I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of two peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general-purpose I/O)
• Synchronous output, provides Set and Clear of several I/O lines in a single write
– Offers visibility of COMMRX and COMMTX signals from the ARM Processor
– Identification of the device revision, sizes of the embedded memories, set of
– Enables software to prevent system access through the ARM Processor’s ICE
– Prevention is made by asserting the NTRST line of the ARM Processor’s ICE
– PIOA has 32 I/O Lines
– PIOB has 32 I/O Lines
– PIOC has 32 I/O Lines
– Input change interrupt
– Glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
peripherals
6462AS–ATARM–03-Jun-09