AT91SAM9G10-CU Atmel, AT91SAM9G10-CU Datasheet - Page 26
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AT91SAM9G10-CU
Manufacturer Part Number
AT91SAM9G10-CU
Description
IC MCU ARM9 SAMPLING 217CBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G10-CU.pdf
(39 pages)
Specifications of AT91SAM9G10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
266MHz
Connectivity
EBI/EMI, I²C, IrDA, ISI, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Controller Family/series
AT91
No. Of I/o's
96
Ram Memory Size
16KB
Cpu Speed
266MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
EBI, SPI, TWI, USART
Maximum Clock Frequency
266 MHz
Number Of Programmable I/os
96
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9G10-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9G10-CU
Manufacturer:
Atmel
Quantity:
1 466
Part Number:
AT91SAM9G10-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
10.3
10.3.1
10.3.1.1
10.3.1.2
10.3.1.3
10.3.1.4
10.3.1.5
26
Peripheral Multiplexing on PIO Lines
AT91SAM9G10
Resource Multiplexing
LCD Controller
EBI
32-bit Data Bus
NAND Flash Interface
Compact Flash Interface
The AT91SAM9G10 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O
lines of the peripheral set.
Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two
peripheral functions, A or B.
page 30
lers. The two columns “Function” and “Comments” have been inserted for the user’s own
comments; they may be used to track how pins are defined in an application.
Note that some output only peripheral functions might be duplicated within the tables.
The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral
mode. If I/O is mentioned, the PIO line resets in input with the pull-up enabled, so that the device
is maintained in a static state as soon as the reset is released. As a result, the bit corresponding
to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this func-
tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released. Note that the pull-up resistor is also enabled in this case.
The LCD Controller can interface with several LCD panels. It supports 4, 8 or 16 bit-per-pixel
without any limitation. Interfacing 24 bit-per-pixel TFTs panel prevents using the SSC0 and the
chip select line 0 of the SPI1.
16 bit-per-pixel TFT panels are interfaced through peripheral B functions, as color data is output
on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on
LCDD2, LCDD10 and LCDD18. Using the peripheral B does not prevent using the SSC0 and
the SPI1 lines.
If not required, the NWAIT function (external wait request) can be deactivated by software,
allowing this pin to be used as a PIO.
Using a 32-bit Data Bus prevents:
Using the NAND Flash interface prevents:
Using the CompactFlash interface prevents:
• using the three Timer Counter channels’ outputs and trigger inputs
• using the SSC2
• using NCS3, NCS6 and NCS7 to access other parallel devices
• using NCS4 and/or NCS5 to access other parallel devices
define how the I/O lines of the peripherals A and B are multiplexed on the PIO Control-
Table 10-2 on page
28,
Table 10-3 on page 29
6462AS–ATARM–03-Jun-09
and
Table 10-4 on