PIC18LF8520-I/PT Microchip Technology, PIC18LF8520-I/PT Datasheet - Page 267
PIC18LF8520-I/PT
Manufacturer Part Number
PIC18LF8520-I/PT
Description
IC MCU FLASH 16KX16 EEPROM80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F8520T-IPT.pdf
(380 pages)
3.PIC18F8520T-IPT.pdf
(16 pages)
4.PIC18F8520T-IPT.pdf
(40 pages)
5.PIC18F8520-IPT.pdf
(2 pages)
Specifications of PIC18LF8520-I/PT
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
No. Of I/o's
68
Eeprom Memory Size
1024Byte
Ram Memory Size
2KB
Cpu Speed
40MHz
No. Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF8520-I/PT
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC18LF8520-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18LF8520-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F8520T-IPT PDF datasheet #2
- PIC18F8520T-IPT PDF datasheet #3
- PIC18F8520T-IPT PDF datasheet #4
- PIC18F8520-IPT PDF datasheet #5
- Current page: 267 of 380
- Download datasheet (7Mb)
24.1
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Instruction Set
W
W
Q1
=
=
PIC18F6520/8520/6620/8620/6720/8720
0x10
0x25
ADD literal to W
[ label ] ADDLW
0
(W) + k
N, OV, C, DC, Z
The contents of W are added to the
8-bit literal ‘k’ and the result is
placed in W.
1
1
literal ‘k’
ADDLW
Read
0000
Q2
k
255
0x15
W
1111
Process
Data
Q3
k
kkkk
Write to W
Q4
kkkk
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
ADD W to f
[ label ] ADDWF
0
d
a
(W) + (f)
N, OV, C, DC, Z
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected. If ‘a’ is ‘1’,
the BSR is used.
1
1
ADDWF
Read
0010
Q2
0x17
0xC2
0xD9
0xC2
f
[0,1]
[0,1]
255
01da
REG, 0, 0
dest
Process
Data
Q3
DS39609B-page 265
f [,d [,a] f [,d [,a]
ffff
destination
Write to
Q4
ffff
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