DSPIC30F6010A-20E/PF Microchip Technology, DSPIC30F6010A-20E/PF Datasheet - Page 13
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DSPIC30F6010A-20E/PF
Manufacturer Part Number
DSPIC30F6010A-20E/PF
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20IP.pdf
(26 pages)
2.DSPIC30F6011A-30IPT.pdf
(6 pages)
3.DSPIC30F6015-30IPT.pdf
(232 pages)
4.DSPIC30F6015-30IPT.pdf
(14 pages)
5.DSPIC30F6015-30IPT.pdf
(12 pages)
6.DSPIC30F6015-30IPT.pdf
(18 pages)
7.DSPIC30F6010A-30IPF.pdf
(22 pages)
Specifications of DSPIC30F6010A-20E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
144KB
Supply Voltage Range
4.5V To 5.5V
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
68
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6010A-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
35.3.2.2.2 SPITBF Status Flag Operation
Figure 35-4:
© 2008 Microchip Technology Inc.
Note 1: Operation for 8-bit mode is shown; the 16-bit mode is similar.
SCK1 Input
(CKP = 0
CKE = 0)
SCK1 Input
(CKP = 1
CKE = 0)
SDO1
Output
SDI1 Input
(SMP = 0)
Input
Sample
(SMP = 0)
SPITBF
SPIRBF
SPI1IF
2: Two SPI1 Clock modes are shown only to demonstrate CKP (SPI1CON1<6>) and CKE (SPI1CON1<8>) bit
3: If there are no pending transmissions or a transmission is in progress, SPI1BUF is transferred to SPI1SR as soon
(2)
(2)
functionality. Any combination of CKP and CKE bits can be selected for module operation.
as the user application writes to SPI1BUF.
User application
writes to
SPI1BUF
SPI1 Slave Mode Timing (Slave Select Pin Disabled)
Section 35. Serial Peripheral Interface (SPI) (Part II)
The SPITBF (SPI1STAT<1>) bit functions differently in the Slave mode of operation than in
Master mode.
If SSEN (SPI1CON1<7>) is cleared, the SPITBF is set when the SPI1BUF is loaded by the user
application. It is cleared when the module transfers SPI1TXB to SPI1SR. This is similar to the
SPITBF bit function in Master mode.
If SSEN is set, the SPITBF is set when the SPI1BUF is loaded by the user application. However,
it is cleared only when the SPI1 module completes data transmission. A transmission will be
aborted when the SS1 pin goes high, but may be retried at a later time. Each data word is held
in SPI1TXB until all bits are transmitted to the receiver.
(3)
bit 7
bit 7
bit 6
bit 5
bit 4
1 instruction cycle latency to set
SPI1IF flag bit
bit 3
(1)
bit 2
SPI1SR to
SPI1RXB
bit 1
bit 0
DS70272B-page 35-13
bit 0
35