AT91SAM7L128-AU Atmel, AT91SAM7L128-AU Datasheet - Page 464

• Manufacturer Part Number: AT91SAM7L128-AU
• Description: MCU ARM7 128K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7L128-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 36MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.55 V ~ 1.8 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 6 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 80
• Ram Memory Size: 6KB
• Cpu Speed: 36MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 128LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 36 MHz
• Operating Supply Voltage: 2.5|3.3 V
• For Use With: AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.6.1
Register Name:
Access Type:
• DIVA, DIVB: CLKA, CLKB Divide Factor
• PREA, PREB
464
DIVA, DIVB
0
1
2-255
0
0
0
0
0
0
0
0
1
1
1
31
23
15
–
–
7
AT91SAM7L128/64 Preliminary
PWM Mode Register
PREA, PREB
0
0
0
0
1
1
1
1
0
0
0
Other
30
22
14
–
–
6
PWM_MR
Read/Write
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
29
21
13
–
–
5
CLKA, CLKB
CLKA, CLKB clock is turned off
CLKA, CLKB clock is clock selected by PREA, PREB
CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
MCK.
MCK/2
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/256
MCK/512
MCK/1024
Reserved
28
20
12
–
–
4
DIVB
DIVA
27
19
11
3
Divider Input Clock
26
18
10
2
PREB
PREA
25
17
9
1
6257A–ATARM–20-Feb-08
24
16
8
0