DSPIC30F6011A-30I/PF Microchip Technology, DSPIC30F6011A-30I/PF Datasheet - Page 48
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DSPIC30F6011A-30I/PF
Manufacturer Part Number
DSPIC30F6011A-30I/PF
Description
IC DSPIC MCU/DSP 132K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F6011A-30IPT.pdf
(234 pages)
4.DSPIC30F6011A-30IPT.pdf
(8 pages)
5.DSPIC30F6011A-30IPT.pdf
(10 pages)
6.DSPIC30F6011A-30IPT.pdf
(6 pages)
7.DSPIC30F6011A-30IPT.pdf
(8 pages)
8.DSPIC30F6011A-30IPT.pdf
(16 pages)
9.DSPIC30F6011A-30IPF.pdf
(236 pages)
Specifications of DSPIC30F6011A-30I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
52
Flash Memory Size
132KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6011A-30I/PF
Manufacturer:
MICROCHIP
Quantity:
966
Company:
Part Number:
DSPIC30F6011A-30I/PF
Manufacturer:
MICROCHIP
Quantity:
316
Company:
Part Number:
DSPIC30F6011A-30I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F6011A/6012A/6013A/6014A
• Execution of a “BRA #literal” instruction or a
• Executing instructions after modifying the PC to
Stack Error Trap:
This trap is initiated under the following conditions:
• The Stack Pointer is loaded with a value which is
• The Stack Pointer is loaded with a value which is
Oscillator Fail Trap:
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
5.3.2
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in
which may require the user to check if other traps are
pending in order to completely correct the fault.
‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.
‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict will occur.
The device is automatically reset in a hard trap conflict
condition. The TRAPR status bit (RCON<15>) is set
when the Reset occurs so that the condition may be
detected in software.
DS70143E-page 48
“GOTO #literal” instruction, where literal is
an unimplemented program memory address
point to unimplemented program memory
addresses. The PC may be modified by loading a
value into the stack and executing a RETURN
instruction
greater than the (user programmable) limit value
written into the SPLIM register (stack overflow)
less than 0x0800 (simple stack underflow)
HARD AND SOFT TRAPS
Figure 5-1
is implemented,
FIGURE 5-1:
5.4
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
Interrupt Request (IRQ) is indicated by the flag bit
being equal to a ‘1’ in an IFSx register. The IRQ will
cause an interrupt to occur if the corresponding bit in
the Interrupt Enable (IECx) register is set. For the
remainder of the instruction cycle, the priorities of all
pending interrupt requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current Program Coun-
ter and the low byte of the processor STATUS register
(SRL), as shown in
STATUS register contains the processor priority level at
the time prior to the beginning of the interrupt cycle.
The processor then loads the priority level for this inter-
rupt into the STATUS register. This action will disable
all lower priority interrupts until the completion of the
Interrupt Service Routine.
AIVT
Interrupt Sequence
IVT
Oscillator Fail Trap Vector
Address Error Trap Vector
Oscillator Fail Trap Vector
Address Error Trap Vector
Reset - GOTO Instruction
Stack Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Math Error Trap Vector
Reset - GOTO Address
Interrupt 52 Vector
Interrupt 53 Vector
Interrupt 52 Vector
Interrupt 53 Vector
Figure
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 0 Vector
Interrupt 1 Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
TRAP VECTORS
© 2011 Microchip Technology Inc.
Reserved
Reserved
Reserved
Reserved
~
~
~
~
~
~
5-2. The low byte of the
0x000000
0x000002
0x000004
0x000014
0x00007E
0x000080
0x000082
0x000084
0x000094
0x0000FE