ATSAM3U2CA-CU Atmel, ATSAM3U2CA-CU Datasheet - Page 110
ATSAM3U2CA-CU
Manufacturer Part Number
ATSAM3U2CA-CU
Description
IC MCU 32BIT 128KB FLSH 100TFBGA
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2CA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
57
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b, 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
3xUSART, TWI, 4xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
57
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U2CA-CU
Manufacturer:
PERICOM
Quantity:
3 186
Part Number:
ATSAM3U2CA-CU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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13.11.4
13.11.4.1
13.11.4.2
13.11.4.3
13.11.4.4
13.11.4.5
110
STRBTEQ
LDRHT
SAM3U Series
LDR and STR, unprivileged
Syntax
Operation
Restrictions
Condition flags
Examples
R4, [R7]
R2, [R2, #8]
Load and Store with unprivileged access.
where:
op
type is one of:
cond
Rt
Rn
offset
These load and store instructions perform the same function as the memory access instructions
with immediate offset, see
these instructions have only unprivileged access even when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as nor-
mal memory access instructions with immediate offset.
In these instructions:
These instructions do not change the flags.
• Rn must not be PC
• Rt must not be SP and must not be PC.
op{type}T{cond} Rt, [Rn {, #offset}]
LDR
STR
B
SB
H
SH
-
; Conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
; Load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access
is one of:
Load Register.
Store Register.
unsigned byte, zero extend to 32 bits on loads.
signed byte, sign extend to 32 bits (LDR only).
unsigned halfword, zero extend to 32 bits on loads.
signed halfword, sign extend to 32 bits (LDR only).
omit, for word.
is an optional condition code, see
is the register to load or store.
is the register on which the memory address is based.
is an offset from Rn and can be 0 to 255.
If offset is omitted, the address is the value in Rn.
“LDR and STR, immediate offset” on page
“Conditional execution” on page
; immediate offset
105. The difference is that
6430D–ATARM–25-Mar-11
100.
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