ATSAM3U2CA-CU Atmel, ATSAM3U2CA-CU Datasheet - Page 73
ATSAM3U2CA-CU
Manufacturer Part Number
ATSAM3U2CA-CU
Description
IC MCU 32BIT 128KB FLSH 100TFBGA
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2CA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
57
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b, 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
3xUSART, TWI, 4xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
57
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U2CA-CU
Manufacturer:
PERICOM
Quantity:
3 186
Part Number:
ATSAM3U2CA-CU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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13.4.4
13.4.4.1
13.4.4.2
13.4.4.3
6430D–ATARM–25-Mar-11
Software ordering of memory accesses
DMB
DSB
ISB
Table 13-5.
1.
2.
The order of instructions in the program flow does not always guarantee the order of the corre-
sponding memory transactions. This is because:
“Memory system ordering of memory accesses” on page 71
memory system guarantees the order of memory accesses. Otherwise, if the order of memory
accesses is critical, software must include memory barrier instructions to force that ordering. The
processor provides the following memory barrier instructions:
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions com-
plete before subsequent memory transactions. See
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transac-
tions complete before subsequent instructions execute. See
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory
transactions is recognizable by subsequent instructions. See
Use memory barrier instructions in, for example:
Address range
0x60000000-
0x7FFFFFFF
0x80000000-
0x9FFFFFFF
0xA0000000-
0xBFFFFFFF
0xC0000000-
0xDFFFFFFF
0xE0000000-
0xE00FFFFF
0xE0100000-
0xFFFFFFFF
• the processor can reorder some memory accesses to improve efficiency, providing this does
• the processor has multiple bus interfaces
• memory or devices in the memory map have different wait states
• some memory accesses are buffered or speculative.
• MPU programming:
not affect the behavior of the instruction sequence.
– Use a DSB instruction to ensure the effect of the MPU takes place immediately at
the end of context switching.
See
The Peripheral and Vendor-specific device regions have no additional access constraints.
“Memory regions, types and attributes” on page 70
Memory region share ability policies (Continued)
Memory region
External RAM
External device
Private Peripheral
Bus
Vendor-specific
device
(2)
Memory type
Normal
Device
Strongly-
ordered
Device
“DMB” on page
(1)
(1)
(1)
(1)
for more information.
“DSB” on page
“ISB” on page
describes the cases where the
Shareability
-
Shareable
Non-
shareable
Shareable
-
156.
SAM3U Series
(1)
(1)
(1)
158.
157.
WBWA
WT
-
-
-
(2)
(2)
73
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