ATXMEGA256A3B-AU Atmel, ATXMEGA256A3B-AU Datasheet - Page 43

MCU AVR 256KB FLASH 64TQFP

ATXMEGA256A3B-AU

Manufacturer Part Number
ATXMEGA256A3B-AU
Description
MCU AVR 256KB FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheet

Specifications of ATXMEGA256A3B-AU

Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
ATXMEGA
No. Of I/o's
49
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
32MHz
Rohs Compliant
Yes
Processor Series
XMEGA
Core
AVR
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
2.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATXMEGA256A3B-AUR
Manufacturer:
Atmel
Quantity:
10 000
8116I–AVR–09/10
Figure 25-1. ADC overview
Each ADC has four MUX selection registers with a corresponding result register. This means
that four channels can be sampled within 1.5 µs without any intervention by the application other
than starting the conversion. The results will be available in the result registers.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop-
agation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each have one ADC. Notation of these peripherals are ADCA and ADCB,
respectively.
Channel A MUX selection
Channel B MUX selection
Channel C MUX selection
Channel D MUX selection
1-64 X
Reference selection
Configuration
ADC
Trigger
Event
Channel C
Channel D
Channel A
Channel B
XMEGA A3B
Register
Register
Register
Register
43

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