ATXMEGA256A3B-AU Atmel, ATXMEGA256A3B-AU Datasheet - Page 44

• Manufacturer Part Number: ATXMEGA256A3B-AU
• Description: MCU AVR 256KB FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-AU

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Controller Family/series: ATXMEGA
• No. Of I/o's: 49
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• Rohs Compliant: Yes
• Processor Series: XMEGA
• Core: AVR
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26. DAC - 12-bit Digital to Analog Converter
26.1
26.2
8116I–AVR–09/10
Features
Overview
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The XMEGA A3B devices features one two-channel, 12-bit, 1 Msps DACs with built-in offset and
gain calibration, see
A DAC converts a digital value into an analog signal. The DAC may use an internal 1.0 voltage
as the upper limit for conversion, but it is also possible to use the supply voltage or any applied
voltage in-between. The external reference input is shared with the ADC reference input.
Figure 26-1. DAC overview
The DAC has one continuous output with high drive capabilities for both resistive and capacitive
loads. It is also possible to split the continuous time channel into two Sample and Hold (S/H)
channels, each with separate data conversion registers.
A DAC conversion may be started from the application software by writing the data conversion
registers. The DAC can also be configured to do conversions triggered by the Event System to
have regular timing, independent of the application software. DMA may be used for transferring
data from memory locations to DAC data registers.
The DAC has a built-in calibration system to reduce offset and gain error when loading with a
calibration value from software.
PORTB has one DAC. Notation of this is DACB.
One DAC with 12-bit resolution
Up to 1 Msps conversion rate for each DAC
Flexible conversion range
Multiple trigger sources
1 continuous output or 2 Sample and Hold (S/H) outputs for each DAC
Built-in offset and gain calibration
High drive capabilities
Low Power Mode
Channel A
Channel B
Register
Register
Figure 26-1 on page
Reference selection
Configuration
Trigger
Event
DAC
44.
XMEGA A3B
Channel A
Channel B
44