AT32UC3A0512-ALUT Atmel, AT32UC3A0512-ALUT Datasheet - Page 156
AT32UC3A0512-ALUT
Manufacturer Part Number
AT32UC3A0512-ALUT
Description
IC MCU AVR32 512KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0512-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
69
Interface Type
Ethernet/I2S/JTAG/SPI/TWI/USART
Number Of Timers
3
Processor Series
AT32UC3x
Core
AVR32
Data Ram Size
64 KB
Maximum Clock Frequency
66 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105, ATAVRRZ600
Minimum Operating Temperature
- 40 C
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0512-ALUT
Manufacturer:
ATMEL
Quantity:
2 155
Part Number:
AT32UC3A0512-ALUT
Manufacturer:
AT
Quantity:
20 000
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21.4.9
21.4.10
21.5
21.5.1
Table 21-1.
21.5.2
32058J–AVR32–04/11
Offset
0x0C
0x1C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
User Interface
0x00C0 - 0x00FF
0x0000 - 0x003F
0x0040 - 0x007F
0x0080 - 0x00BF
0x0100 - 0x013F
Address Range
Priority
Error Handling
Memory Map Overview
Channel Memory Map
Register Map Overview
-
-
Memory Address Reload Register
Transfer Counter Reload Register
If more then one PDCA channel is requesting transfer at a given time, the PDCA channels are
prioritized by their channel number. Channels with lower numbers have priority over channels
with higher numbers, giving channel 0 the highest priority.
If the memory address is set to point to an invalid location in memory, an error will occur when
the PDCA tries to perform a transfer. When an error occurs, the Transfer Error flag (TERR) in
the Interrupt Status Register will be set and the DMA channel that caused the error will be
stopped. In order to restart the channel, the user must program the Memory Address Register to
a valid address and then write the Error Clear bit (ECLR) in the Control Register (CR) to ‘1’. An
interrupt can optionally be triggered on errors by writing the TERR-bit in the Interrupt Enable
Register (IER) to ‘1’.
Note:
Memory Address Register
Peripheral Select Register
Transfer Counter Register
Interrupt Enable Register
Control Register
Status Register
Mode Register
The number of channels is implementation specific. See part documentation for details.
Register
DMA channel n-1 configuration registers
DMA channel 0 configuration registers
DMA channel 1 configuration registers
DMA channel 2 configuration registers
DMA channel 3 configuration registers
DMA channel 4 configuration registers
Register Name
MARR
TCRR
MAR
PSR
TCR
MR
IER
CR
SR
Contents
-
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Write-only
Write-only
Access
AT32UC3A
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
*
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