AT32UC3A0512-ALUT Atmel, AT32UC3A0512-ALUT Datasheet - Page 517
AT32UC3A0512-ALUT
Manufacturer Part Number
AT32UC3A0512-ALUT
Description
IC MCU AVR32 512KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0512-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
69
Interface Type
Ethernet/I2S/JTAG/SPI/TWI/USART
Number Of Timers
3
Processor Series
AT32UC3x
Core
AVR32
Data Ram Size
64 KB
Maximum Clock Frequency
66 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105, ATAVRRZ600
Minimum Operating Temperature
- 40 C
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0512-ALUT
Manufacturer:
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Quantity:
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Figure 30-18. Example of an IN Endpoint with 2 Data Banks
30.7.2.12.2 Detailed Description
32058J–AVR32–04/11
TXINI
FIFOCON
SW
write data to CPU
The data is written by the firmware, following the next flow:
If the endpoint uses several banks, the current one can be written by the firmware while the pre-
vious one is being read by the host. Then, when the firmware clears FIFOCON, the following
bank may already be free and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The KILLBK bit is used to kill the last written
bank. The best way to manage this abort is to apply the algorithm represented on
•when the bank is empty, TXINI and FIFOCON are set, what triggers an EPXINT interrupt if
•the firmware acknowledges the interrupt by clearing TXINI;
•the firmware writes the data into the current bank by using the USB Pipe/Endpoint X FIFO
•the firmware allows the controller to send the bank and switches to the next bank (if any) by
BANK 0
TXINE = 1;
Data register (USB_FIFOX_DATA), until all the data frame is written or the bank is full (in
which case RWALL is cleared by hardware and BYCT reaches the endpoint size);
clearing FIFOCON.
SW
IN
SW
write data to CPU
BANK 1
(bank 0)
DATA
SW
HW
ACK
SW
write data to CPU
IN
BANK0
(bank 1)
DATA
AT32UC3A
ACK
Figure
30-19.
517
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