P89LPC9361FDH,518 NXP Semiconductors, P89LPC9361FDH,518 Datasheet - Page 43
P89LPC9361FDH,518
Manufacturer Part Number
P89LPC9361FDH,518
Description
MCU 80C51 16KB FLASH 28TSSOP
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet
1.P89LPC9351FA112.pdf
(94 pages)
Specifications of P89LPC9361FDH,518
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
28-TSSOP
Core Processor
8051
Core Size
8-Bit
Speed
18MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
26
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x8b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
P89LPC
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8 bit, 4 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935289566518
NXP Semiconductors
P89LPC9331_9341_9351_9361
Product data sheet
7.22.7 Alternating output mode
7.22.8 PLL operation
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating
pairs for bridge drive control. In this mode the output of these PWM channels are
alternately gated on every counter cycle.
The PWM module features a Phase Locked Loop that can be used to generate a
CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module
provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal
frequency is 1 MHz or higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and
generates an output signal of 32 times the input frequency. This signal is used to clock the
timer. The user will have to set a divider that scales PCLK by a factor from 1 to 16. This
divider is found in the SFR register TCR21. The PLL frequency can be expressed as
shown in
Where: N is the value of PLLDV3:0.
PLL frequency
Fig 10. Symmetrical PWM
Fig 11. Alternate output mode
Equation
compare value
=
All information provided in this document is subject to legal disclaimers.
non-inverted
timer value
----------------- -
(
PCLK
N
inverted
1:
TOR2
+
1
Rev. 5 — 10 January 2011
0
)
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
002aaa895
TOR2
COMPARE VALUE A (or C)
COMPARE VALUE B (or D)
0
PWM OUTPUT (OCA or OCC)
PWM OUTPUT (OCB or OCD)
TIMER VALUE
002aaa894
© NXP B.V. 2011. All rights reserved.
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