LPC1111FHN33/101,5 NXP Semiconductors, LPC1111FHN33/101,5 Datasheet - Page 21
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LPC1111FHN33/101,5
Manufacturer Part Number
LPC1111FHN33/101,5
Description
IC MCU 32BIT 8KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC1100r
Datasheets
1.LPC1114FHN333015.pdf
(2 pages)
2.LPC1114FHN333015.pdf
(66 pages)
3.LPC1114FHN333015.pdf
(66 pages)
Specifications of LPC1111FHN33/101,5
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC11
Core
ARM Cortex M0
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Number Of Programmable I/os
28
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M0
Family Name
LPC1100
Maximum Speed
50 MHz
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4957
935290771551
935290771551
NXP Semiconductors
LPC1111_12_13_14
Product data sheet
Fig 5.
(1) LQFP48/PLCC44 packages only.
0.5 GB
LPC1111/12/13/14 memory map
0 GB
4 GB
1 GB
7.5.1 Features
7.5 Nested Vectored Interrupt Controller (NVIC)
4 kB SRAM (LPC1111/12/13/14/201/202)
8 kB SRAM (LPC1113/14/301/302)
2 kB SRAM (LPC1111/12/101/102)
16 kB on-chip flash (LPC1112)
32 kB on-chip flash (LPC1114)
24 kB on-chip flash (LPC1113)
8 kB on-chip flash (LPC1111)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
LPC1111/12/13/14
private peripheral bus
•
AHB peripherals
16 kB boot ROM
APB peripherals
Controls system exceptions and peripheral interrupts.
reserved
reserved
reserved
reserved
reserved
reserved
reserved
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 10 February 2011
0xFFFF FFFF
0xE010 0000
0xE000 0000
0x5020 0000
0x5000 0000
0x4008 0000
0x4000 0000
0x2000 0000
0x1FFF 4000
0x1FFF 0000
0x1000 2000
0x1000 1000
0x1000 0800
0x1000 0000
0x0000 8000
0x0000 6000
0x0000 4000
0x0000 2000
0x0000 0000
active interrupt vectors
22
18
17
16
15
14
9
8
7
6
5
4
3
2
1
0
12-15
8-11
4-7
0-3
32-bit ARM Cortex-M0 microcontroller
LPC1111/12/13/14
32-bit counter/timer 1
127-16 reserved
32-bit counter/timer 0
16-bit counter/timer 1
16-bit counter/timer 0
AHB peripherals
APB peripherals
31-23 reserved
21-19 reserved
13-10 reserved
system control
flash controller
GPIO PIO3
GPIO PIO2
GPIO PIO1
GPIO PIO0
IOCONFIG
reserved
reserved
I
SPI1
2
ADC
UART
PMU
WDT
SPI0
C-bus
0x0000 00C0
0x0000 0000
(1)
0x4008 0000
0x4005 C000
0x4005 8000
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
0x4003 C000
0x4003 8000
0x4002 8000
0x4002 4000
0x4002 0000
0x4001 C000
0x4001 8000
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
0x4000 4000
0x4000 0000
© NXP B.V. 2011. All rights reserved.
0x5020 0000
0x5004 0000
0x5003 0000
0x5002 0000
0x5001 0000
0x5000 0000
002aae699
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