P89V51RB2BBC,557 NXP Semiconductors, P89V51RB2BBC,557 Datasheet - Page 18

• Manufacturer Part Number: P89V51RB2BBC,557
• Description: IC 80C51 MCU 1024 RAM 44TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V51RB2BBC,557

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P89V5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1017 - BOARD 44-ZIF PLCC SOCKET
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935277723557; P89V51RB2BBC; P89V51RB2BBC

NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
DPTR points to 0A0H and data in ‘A’ is written to address 0A0H of the expanded RAM
rather than external memory. Access to external memory higher than 2FFH using the
MOVX instruction will access external memory (0300H to FFFFH) and will perform in the
same way as the standard 8051, with P0 and P2 as data/address bus, and P3.6 and P3.7
as write and read timing signals.
When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051.
Using MOVX @Ri provides an 8-bit address with multiplexed data on Port 0. Other output
port pins can be used to output higher order address bits. This provides external paging
capabilities. Using MOVX @DPTR generates a 16-bit address. This allows external
addressing up the 64 kB. Port 2 provides the high-order eight address bits (DPH), and
Port 0 multiplexes the low order eight address bits (DPL) with data. Both MOVX @Ri and
MOVX @DPTR generates the necessary read and write signals (P3.6 - WR and P3.7 -
RD) for external memory use.
with EXTRAM bit.
The stack pointer (SP) can be located anywhere within the 256 B of internal RAM (lower
128 B and upper 128 B). The stack pointer may not be located in any part of the expanded
RAM.
Table 9.
[1]
AUXR
EXTRAM = 0
EXTRAM = 1
Access limited to ERAM address within OSPI to 0FFH; cannot access 100H to 02FFH.
External data memory RD, WR with EXTRAM bit
MOVX @DPTR, A or MOVX A,
@DPTR
ADDR < 0300H
RD/WR not
asserted
RD/WR asserted
Rev. 05 — 12 November 2009
Table 9
ADDR
RD/WR asserted
RD/WR asserted
shows external data memory RD, WR operation
P89V51RB2/RC2/RD2
0300H
8-bit microcontrollers with 80C51 core
MOVX @Ri, A or MOVX A, @Ri
ADDR = any
RD/WR not asserted
RD/WR asserted
[1]
© NXP B.V. 2009. All rights reserved.
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