p89v51rb2 NXP Semiconductors, p89v51rb2 Datasheet
p89v51rb2
Available stocks
Related parts for p89v51rb2
p89v51rb2 Summary of contents
Page 1
... The P89V51RB2/RC2/RD2 are 80C51 microcontrollers with 16/32/64 kB flash and 1024 B of data RAM. A key feature of the P89V51RB2/RC2/RD2 is its X2 mode option. The design engineer can choose to run the application with the conventional 80C51 clock rate (12 clocks per machine cycle) or select the X2 mode (six clocks per machine cycle) to achieve twice the throughput at the same clock frequency. Another way to benefi ...
Page 2
... P89V51RD2FA PLCC44 P89V51RD2FBC TQFP44 P89V51RD2BN DIP40 P89V51RD2FN DIP40 3.1 Ordering options Table 2. Type number P89V51RB2FA P89V51RB2FN P89V51RB2BBC P89V51RC2FA P89V51RC2FBC P89V51RC2FN P89V51RD2FA P89V51RD2FBC P89V51RD2BN P89V51RD2FN P89V51RB2_RC2_RD2_4 Product data sheet Description plastic leaded chip carrier; 44 leads plastic dual in-line package; 40 leads (600 mil) plastic thin quad flat package; 44 leads; body 10 plastic leaded chip carrier ...
Page 3
... Product data sheet HIGH PERFORMANCE 80C51 CPU 16/32/64 kB CODE FLASH internal bus 1 kB DATA RAM PORT 3 PORT 2 PORT 1 PORT 0 OSCILLATOR Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core TXD UART RXD TIMER 0 T0 TIMER TIMER 2 T2EX SPICLK MOSI SPI ...
Page 4
... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. PLCC44 pin configuration P89V51RB2_RC2_RD2_4 Product data sheet P89V51RB2/RC2/RD2 P1.5/MOSI/CEX2 7 8 P1.6/MISO/CEX3 P1.7/SCK/CEX4 9 RST 10 P3.0/RXD 11 P89V51RB2FA 12 n.c. P89V51RC2FA P89V51RD2FA P3.1/TXD 13 P3.2/INT0 14 15 P3.3/INT1 16 P3.4/T0 P3.5/T1 17 Rev. 04 — 1 May 2007 8-bit microcontrollers with 80C51 core 39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0 ...
Page 5
... P89V51RD2FN 12 P3.2/INT0 P3.3/INT1 13 P3.4/ P3.5/T1 P3.6/WR 16 P3.7/RD 17 XTAL2 18 19 XTAL1 002aaa811 1 P1.5/MOSI/CEX2 P1.6/MISO/CEX3 2 P1.7/SCK/CEX4 3 RST 4 5 P3.0/RXD P89V51RB2BBC P89V51RC2FBC n.c. 6 P89V51RD2FBC P3.1/TXD 7 8 P3.2/INT0 9 P3.3/INT1 P3.4/T0 10 P3.5/T1 11 Rev. 04 — 1 May 2007 8-bit microcontrollers with 80C51 core P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0 ...
Page 6
... NXP Semiconductors 5.2 Pin description Table 3. P89V51RB2/RC2/RD2 pin description Symbol Pin DIP40 TQFP44 P0.0 to P0.7 P0.0/AD0 39 37 P0.1/AD1 38 36 P0.2/AD2 37 35 P0.3/AD3 36 34 P0.4/AD4 35 33 P0.5/AD5 34 32 P0.6/AD6 33 31 P0.7/AD7 32 30 P1.0 to P1.7 P1.0/ P1.1/T2EX 2 41 P89V51RB2_RC2_RD2_4 Product data sheet P89V51RB2/RC2/RD2 Type Description PLCC44 I/O Port 0: Port 8-bit open drain bidirectional I/O port. ...
Page 7
... NXP Semiconductors Table 3. P89V51RB2/RC2/RD2 pin description Symbol Pin DIP40 TQFP44 P1.2/ECI 3 42 P1.3/CEX0 4 43 P1.4/SS/CEX1 5 44 P1.5/MOSI CEX2 P1.6/MISO CEX3 P1.7/SCK CEX4 P2.0 to P2.7 P2.0/ P2.1/ P2.2/A10 23 20 P2.3/A11 24 21 P2.4/A12 25 22 P89V51RB2_RC2_RD2_4 Product data sheet P89V51RB2/RC2/RD2 …continued Type Description ...
Page 8
... NXP Semiconductors Table 3. P89V51RB2/RC2/RD2 pin description Symbol Pin DIP40 TQFP44 P2.5/A13 26 23 P2.6/A14 27 24 P2.7/A15 28 25 P3.0 to P3.7 P3.0/RXD 10 5 P3.1/TXD 11 7 P3.2/INT0 12 8 P3.3/INT1 13 9 P3.4/ P3.5/ P3.6/ P3.7/ PSEN 29 26 P89V51RB2_RC2_RD2_4 Product data sheet P89V51RB2/RC2/RD2 …continued Type Description PLCC44 29 I/O P2.5 — Port 2 bit 5. ...
Page 9
... NXP Semiconductors Table 3. P89V51RB2/RC2/RD2 pin description Symbol Pin DIP40 TQFP44 RST ALE/PROG 17, 28, 39 XTAL1 19 15 XTAL2 [1] ALE loading issue: When ALE pin experiences higher loading (>30 pF) during the reset, the microcontroller may accidentally enter into modes other than normal working mode ...
Page 10
... P89V51RB2_RC2_RD2_4 Product data sheet P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Rev. 04 — 1 May 2007 © NXP B.V. 2007. All rights reserved. ...
Page 11
Table 4. Special function registers * indicates SFRs that are bit addressable Name Description SFR address Bit address ACC* Accumulator AUXR Auxiliary function register AUXR1 Auxiliary function register 1 Bit address B* B register CCAP0H Module 0 Capture HIGH CCAP1H ...
Page 12
Table 4. Special function registers …continued * indicates SFRs that are bit addressable Name Description SFR address FST Flash Status Register Bit address IEN0* Interrupt Enable 0 Bit address IEN1* Interrupt Enable 1 Bit address IP0* Interrupt Priority IP0H Interrupt ...
Page 13
Table 4. Special function registers …continued * indicates SFRs that are bit addressable Name Description SFR address SADDR Serial Port Address Register SADEN Serial Port Address Enable Bit address SPCTL SPI Control Register SPCFG SPI Configuration Register SPDAT SPI Data ...
Page 14
... SS and RST to avoid programming at an indeterminate location, DD Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Table 5. Addresses above 1FFFH user code (in block 0) through Figure 5. Note that ...
Page 15
... The POF flag in the PCON register is set to indicate an initial power up condition. The POF flag will remain active until cleared by software. Following a power-on or external reset the P89V51RB2/RC2/RD2 will force the SWR and BSEL bits (FCF[1:0]) = 00. This causes the boot block to be mapped into the lower code memory and the device will execute the ISP code in the boot block and attempt to auto baud to the host ...
Page 16
... The data RAM has 1024 B of internal memory. The device can also address for external data memory. 6.2.7 Expanded data RAM addressing The P89V51RB2/RC2/RD2 has RAM. See memory structure” on page The device has four sections of internal data memory: 1 ...
Page 17
... When ‘1’, every MOVX @Ri/@DPTR instruction targets external data memory by default. AO ALE off: disables/enables ALE results in ALE emitted constant rate of active only during a MOVX or MOVC. Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core EXTRAM the oscillator frequency ...
Page 18
... External data memory RD, WR with EXTRAM bit MOVX @DPTR MOVX A, @DPTR ADDR < 0300H ADDR RD/WR not RD/WR asserted asserted RD/WR asserted RD/WR asserted Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core [1] MOVX @Ri MOVX A, @Ri 0300H ADDR = any RD/WR not asserted RD/WR asserted © NXP B.V. 2007. All rights reserved ...
Page 19
... FFH EXPANDED RAM 768 B 80H 7FH (INDIRECT ADDRESSING) 00H 000H FFFFH 0300H EXPANDED RAM Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core FFH (DIRECT (INDIRECT ADDRESSING) ADDRESSING) SPECIAL FUNCTION UPPER 128 B REGISTERS (SFRs) 80H INTERNAL RAM LOWER 128 B INTERNAL RAM ...
Page 20
... Flash memory IAP 6.3.1 Flash organization The P89V51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block. ISP capability second 8 kB block, is provided to allow the user code to be programmed in-circuit through the serial port. There are three methods of erasing or programming of the flash memory that may be used. First, the flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point (IAP) ...
Page 21
... This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the P89V51RB2/RC2/RD2 to establish the baud rate. The ISP firmware provides auto-echo of received characters. Once baud rate initialization has been performed, the ISP fi ...
Page 22
... Following the next reset the device will enter the SoftICE mode. Will erase user code memory, erase device serial number. :00000002cc Where: xxxxxx = required field but value is a ‘don’t care’ checksum Example: :00000002FE Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core © NXP B.V. 2007. All rights reserved ...
Page 23
... MSB first eeee = ending address, MSB first ff = subfunction 00 = display data 01 = blank check cc = checksum Subfunction codes: Example: :0500000400001FFF00D9 (display from 0000H to 1FFFH) Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core © NXP B.V. 2007. All rights reserved ...
Page 24
... Where: xxxxxx = required field but value is a ‘don’t care’ verify serial number function ss..ss = serial number contents cc = checksum Example: :03000008010203EF (verify s/n = 010203) Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core © NXP B.V. 2007. All rights reserved ...
Page 25
... Reset and run user code :xxxxxx0Bcc Where: xxxxxx = required field but value is a ‘don’t care’ Reset and run user code cc = checksum Example: :0000000BF5 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Table 13. © NXP B.V. 2007. All rights reserved ...
Page 26
... ACC = byte to program Return parameter(s): ACC = 00 = pass ACC = !00 = fail Input parameters 03H DPH = memory address MSB DPL = memory address LSB Return parameter(s): ACC = device data Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core © NXP B.V. 2007. All rights reserved ...
Page 27
... DPH = sector address high byte DPL = sector address low byte Return parameter(s): ACC = 00 = pass ACC = !00 = fail Table the oscillator frequency. 6 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core and Table 15). © NXP B.V. 2007. All rights reserved ...
Page 28
... Timer 0 Run control bit. Set/cleared by software to turn Timer/counter 0 on/off. IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge/low level is detected. Cleared by hardware when the interrupt is processed software. Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core T1M0 T0GATE T0C/T 8048 timer ‘ ...
Page 29
... IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level that triggers external interrupt TRn Figure 9. Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Figure 8 shows mode 0 operation. overflow TLn THn TFn (5-bits) (8-bits) ...
Page 30
... Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in mode 3, the P89V51RB2/RC2/RD2 can look like it has an additional Timer. Note: When Timer mode 3, Timer 1 can be turned on and off by switching it into and out of its own mode 3. It can still be used by the serial port as a baud rate generator any application not requiring an interrupt ...
Page 31
... Receive clock flag. When set, causes the UART to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overfl used for the receive clock. Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core overflow TL0 ...
Page 32
... Reserved for future use. Should be set to ‘0’ by user programs. T2OE Timer 2 Output Enable bit. Used in programmable clock-out mode only. DCEN Down Count Enable bit. When set, this allows Timer configured as an up/down counter. Figure Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core / 6) osc / 12 osc ...
Page 33
... TR2 capture RCAP2L RCAP2H control EXEN2 and Table 23). When reset is applied, DCEN = 0 and Timer 2 will default to shows Timer 2 counting up automatically (DCEN = 0). Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core TH2 TF2 (8-bits) interrupt EXF2 002aaa523 / 6 pulses. Since once osc © ...
Page 34
... RCAP2L RCAP2H control EXEN2 RCAP2H RCAP2L (C/ frequency of signal on T2 pin osc 14, DCEN = 1 and Timer 2 is enabled to count up or down. This mode allows pin Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core TH2 TF2 (8-bits) interrupt EXF2 002aaa524 © NXP B.V. 2007. All rights reserved. ...
Page 35
... FFH FFH TL2 TH2 (8-bits) (8-bits) control TR2 RCAP2L RCAP2H (up-counting reload value) RCAP2H RCAP2L Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core toggle EXF2 underflow TF2 overflow count direction down T2EX pin 002aaa525 Equation 2: Section 6.6 “ ...
Page 36
... Timer 2 in baud rate generator mode: C/ control C/ TR2 detector EXF2 control EXEN2 OscillatorFrequency – RCAP2H RCAP2L Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core TL2 TH2 TX/RX baud rate (8-bits) (8-bits) reload RCAP2L RCAP2H timer 2 interrupt 002aaa526 1 the oscillator ...
Page 37
... Timer 2 generated commonly used baud rates Osc freq 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 6 MHz 6 MHz Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Table 24 shows commonly used baud baud rate) Timer 2 RCAP2H RCAP2L ...
Page 38
... Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in modes 2 and 3. Set or clear by software as desired. Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core 1 of the CPU clock frequency, as determined 32 overflow rate. ...
Page 39
... SCON - Serial port control register (address 98H) SM0/SM1 mode definition UART mode 0: shift register 1: 8-bit UART 2: 9-bit UART 3: 9-bit UART Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core …continued Baud rate CPU clock / 6 variable CPU clock / 32 or CPU clock / 16 variable © ...
Page 40
... Given address allows multiple slaves to be recognized while excluding others. This device uses the methods presented in ‘Broadcast’ address has been received or not. P89V51RB2_RC2_RD2_4 Product data sheet P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Figure 16 to determine if a ‘Given’ or Rev. 04 — 1 May 2007 © ...
Page 41
... UART to detect 'given address' in received data saddr(7) saden(7) rx_byte( saddr(0) saden(0) rx_byte(0) logic used by UART to detect 'given address' in received data multiprocessor communications is enabled Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core given_address_match broadcast_address_match 002aaa527 © NXP B.V. 2007. All rights reserved. (4) ( ...
Page 42
... Wake-up from Idle mode (slave mode only) 6.7.2 SPI description The SPI allows high-speed synchronous data transfer between the P89V51RB2/RC2/RD2 and peripheral devices or between several P89V51RB2/RC2/RD2 devices. shows the correspondence between master and slave SPI devices. The SCK pin is the P89V51RB2_RC2_RD2_4 ...
Page 43
... MSTR Master/slave select master mode slave mode. CPOL Clock polarity SCK is high when idle (active LOW SCK is low when idle (active HIGH). Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Figure 18 MSB slave LSB 8-BIT SHIFT REGISTER 002aaa528 4 ...
Page 44
... This bit is cleared by software. - Reserved for future use. Should be set to ‘0’ by user programs MSB MSB Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core …continued below. below. SCK = f divided by osc 128 ...
Page 45
... WDT. Two SFRs (WDTC and WDTD) control WDTD) 344064 344064 clks WDT COUNTER UPPER BYTE WDTC WDTD Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core LSB LSB 002aaa530 CLK(XTAL1) ...
Page 46
... Watchdog timer refresh. Set by software to force a WDT reset. SWDT Start watchdog timer, when set starts the WDT. When cleared, stops the WDT. 16 bits MODULE0 MODULE1 MODULE2 MODULE3 MODULE4 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core WDRE WDTS WDT 1 1 the oscillator frequency, ...
Page 47
... When a module is used in the PWM mode these registers are used to control the duty cycle of the output. P89V51RB2_RC2_RD2_4 Product data sheet Figure 22. Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Figure 22). © NXP B.V. 2007. All rights reserved ...
Page 48
... PCA Enable Counter Overflow Interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function. CMOD - PCA counter mode register (address D9H) count pulse select CPS0 Select PCA input 0 0 Internal clock, f Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core CCF4 CCF3 CCF2 CCF1 CCF0 IEN0.6 IEN0 ...
Page 49
... Capture Negative, CAPNn = 1 enables negative edge capture. MATn Match. When MATn = 1 a match of the PCA counter with this module’s compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core / 6 osc 4 3 ...
Page 50
... Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core ECCFn Module function 0 no operation x 16-bit capture by a positive-edge trigger on CEXn x 16-bit capture by a negative-edge trigger on CEXn x 16-bit capture by any transition on CEXn x 16-bit software timer ...
Page 51
... P89V51RB2_RC2_RD2_4 Product data sheet - CCF4 CCF3 CCF2 (to CCFn) capture CAPPn CAPNn MATn TOGn 0 0 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core CCON CCF1 CCF0 (D8H) PCA interrupt PCA timer/counter CH CL CCAPnH CCAPnL CCAPMn PWMn ECCFn (DAH to DEH) ...
Page 52
... COMPARATOR CH CL PCA timer/counter - ECOMn CAPPn CAPNn 0 0 (Figure 25) the CEX output (on port 1) associated with the PCA module will Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core CCF3 CCF2 CCF1 CCF0 (to CCFn) MATn TOGn PWMn ECCFn © ...
Page 53
... PCA timer/counter - ECOMn CAPPn CAPNn 0 0 CCAPnH CCAPnL 8-BIT COMPARATOR CL PCA timer/counter CAPNn MATn TOGn Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core CCF3 CCF2 CCF1 CCF0 (to CCFn) MATn TOGn PWMn ECCFn (Figure 26). Output frequency 0 CL CCAPnL CL ...
Page 54
... CCAP4L,#00 ;Next compare value is within 255 counts of current PCA timer value CCAP4H,CH EA ;Re-enable interrupts Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Figure 26 shows a diagram of how the 16 count of the PCA © NXP B.V. 2007. All rights reserved ...
Page 55
... Product data sheet Vector address Interrupt enable 0003H EX0 004BH EBO 000BH ET0 0013H EX1 001BH ET1 0033H EC 0023H ES 002BH ET2 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Figure 27). Interrupt Service priority priority PX0/H 1 (highest) PBO/H 2 PT0/H 3 PX1/H 4 PT1/H 5 PPCH 6 ...
Page 56
... IE and IEA registers IE0 IE1 global individual disable enables IEN0 - Interrupt enable register 0 (address A8H) bit allocation ET2 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core registers ET1 EX1 highest priority interrupt interrupt polling sequence lowest ...
Page 57
... External interrupt 1 priority LOW bit. PT0 Timer 0 interrupt priority LOW bit. PX0 External interrupt 0 priority LOW bit. IP0H - Interrupt priority 0 high register (address B7H) bit allocation PPCH PT2H Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core EBO - PT1 ...
Page 58
... IP1H - Interrupt priority 1 high register (address F7H) bit description Symbol Description - Reserved for future use. Should be set to ‘0’ by user programs. PBOH Brownout interrupt priority bit. - Reserved for future use. Should be set to ‘0’ by user programs. Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core PBO - - 4 3 ...
Page 59
... PCON) MOV PCON, #01H Power-down Software (Set PD bit in mode PCON) MOV PCON, #02H P89V51RB2_RC2_RD2_4 Product data sheet P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core , the interrupt service routine program execution IH line is restored to its normal operating voltage. Be sure to hold DD State of MCU CLK is running. Interrupts, serial port and timers/counters are active ...
Page 60
... Table 57 shows the typical values for C1 and C2 vs. crystal type for various Recommended values for C1 and C2 by crystal type Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core and V specifications ...
Page 61
... Reserved for future use. Should be set to ‘0’ by user programs. EDC Enable double clock. - Reserved for future use. Should be set to ‘0’ by user programs. Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core XTAL2 XTAL1 V SS 002aaa546 Clock double mode (X2) Clocks per Max ...
Page 62
... V; XTAL1, RST 4.5 V; ports except DD PSEN, ALE I = 100 1 3 4.5 V; port 0, PSEN, ALE 200 3 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Min Max 55 +125 65 +150 0.5 +14 0 1.5 Min Typ Max [1] 10000 - ...
Page 63
... OL may exceed the related specification. Pins are not guaranteed to sink current greater than the OH on ALE and PSEN to momentarily fall below the V OH Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Min Typ Max [5] V ...
Page 64
... Maximum active I DD (2) Maximum idle I DD (3) Typical active I DD (4) Typical idle I DD Fig 30. I vs. frequency DD P89V51RB2_RC2_RD2_4 Product data sheet P89V51RB2/RC2/RD2 10 20 Rev. 04 — 1 May 2007 8-bit microcontrollers with 80C51 core 002aaa813 (1) (2) (3) ( internal clock frequency (MHz) © NXP B.V. 2007. All rights reserved. ...
Page 65
... QVWH t RD LOW to address float time RLAZ HIGH to ALE HIGH time WHLH [ cy(clk) osc [2] Calculated values are for 6-clock mode only. P89V51RB2_RC2_RD2_4 Product data sheet P89V51RB2/RC2/RD2 [1][ Conditions Min X1 mode 0 X2 mode 0 IAP 0.25 2T cy(clk) T ...
Page 66
... P89V51RB2_RC2_RD2_4 Product data sheet t LHLL t LLIV t LLPL t PLIV t PLAZ t LLAX INSTR IN t AVIV A8 to A15 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core t PLPH t PXAV t PXIZ t PXIX A15 002aaa548 © NXP B.V. 2007. All rights reserved ...
Page 67
... P2[0] to P2[ A15 from DPF t t WLWH LLWL t LLAX t QVWH DATA OUT t AVWL P2[7: A15 from DPH Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core t WHLH t RHDZ from PCL A0 to A15 from PCH t WHLH t WHQX from PCL INSTR IN ...
Page 68
... CHCL CLCX Oscillator 40 MHz Min Max 0.3 - 117 - 117 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Variable Min Max 0.35T 0.65T cy(clk) cy(clk) 0.35T 0.65T cy(clk) cy(clk CHCX t CLCH T cy(clk) 002aaa907 Variable ...
Page 69
... Figure 36, 37, 38, 39 see Figure 36, 37, 38, 39 see Figure 36, 37, 38, 39 see Figure 36, 37, 38, 39 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core set TI valid valid valid valid set RI Variable clock f osc Min Max Min 0 ...
Page 70
... SPIF SPIR t SPICLKL t SPICLKH t t SPIDSU SPIDH MSB/LSB SPIDV SPIOH master MSB/LSB out Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core SPIR LSB/MSB SPIDV SPIR master LSB/MSB out 002aaa908 LSB/MSB SPIDV SPIDV t SPIR master LSB/MSB out 002aaa909 © ...
Page 71
... SPIR t SPICLKL t SPICLKH t SPIR t SPICLKL t SPICLKH t SPIOH t SPIDV slave MSB/LSB out t t SPIDSU SPIDH MSB/LSB in Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core t SPIR t SPILAG t SPIOH slave LSB/MSB out not defined t t SPIDSU SPIDH LSB/MSB in 002aaa910 t SPIR t SPILAG t SPIOH ...
Page 72
... DUT V DD (n.c.) clock signal All other pins disconnected test condition, Active mode DD (n.c.) clock signal All other pins disconnected test condition, Idle mode DD Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core to tester C L 002aaa555 RST ...
Page 73
... Fig 43. I P89V51RB2_RC2_RD2_4 Product data sheet V DD RST (n.c.) XTAL2 XTAL1 V SS All other pins disconnected test condition, Power-down mode DD Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core = 002aaa558 © NXP B.V. 2007. All rights reserved. ...
Page 74
... 1.70 0.53 0.36 52.5 14.1 1.14 0.38 0.23 51.5 13.7 0.067 0.021 0.014 2.067 0.56 0.045 0.015 0.009 2.028 0.54 REFERENCES JEDEC JEITA MO-015 SC-511-40 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core 3.60 15.80 17.42 2.54 15.24 3.05 15.24 15.90 0.14 0.62 0.69 0.1 0.6 0.12 0.60 0.63 EUROPEAN ...
Page 75
... 2.5 scale (1) ( 0.45 0.18 10.1 10.1 12.15 12.15 0.8 0.30 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core detail 0.75 1.2 1 0.2 0.2 0.1 0.45 0.8 EUROPEAN PROJECTION SOT376 (1) ...
Page 76
... 0.81 16.66 16.66 16.00 16.00 17.65 1.27 0.66 16.51 16.51 14.99 14.99 17.40 0.032 0.656 0.656 0.63 0.63 0.695 0.05 0.026 0.650 0.650 0.59 0.59 0.685 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core detail 17.65 1.22 1.44 0.18 0.18 0.1 17.40 1.07 1.02 0.695 ...
Page 77
... In-Application Programming In-System Programming Microcontroller Unit Programmable Counter Array Pulse Width Modulator Resistance-Capacitance Special Function Register Serial Peripheral Interface Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core © NXP B.V. 2007. All rights reserved ...
Page 78
... The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where applicable. Added new part types P89V51RB2FA, P89V51RB2FN, P89V51RC2FN, and P89V51RD2FN; removed part types P89V51RB2BA and P89V51RC2BN. Product data ...
Page 79
... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 04 — 1 May 2007 P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core © NXP B.V. 2007. All rights reserved ...
Page 80
... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: P89V51RB2_RC2_RD2_4 All rights reserved. Date of release: 1 May 2007 ...