LH79525N0Q100A1;55 NXP Semiconductors, LH79525N0Q100A1;55 Datasheet - Page 22

• Manufacturer Part Number: LH79525N0Q100A1;55
• Description: IC ARM7 BLUESTREAK MCU 176LQFP
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7r

Specifications of LH79525N0Q100A1;55

• Package / Case: 176-LQFP
• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 76.2MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LH795
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 50.803 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4333; 935285052557; LH79525N0Q100A1

LH79524/LH79525
DMA Controller
ble peripherals. The LCD controller uses its own DMA
port, connecting directly to memory for retrieving dis-
play data.
• Simultaneous servicing of up to 4 data streams
• Three transfer modes are supported:
• Identical source and destination capabilities
• Transfer Size Programmable (byte, half-word, word)
• Burst Size Programmable
• Address Increment or Address Freeze
• Transfer Error interrupt for each stream
• 16-word FIFO array with pack and unpack logic
transfers from input to output.
Color LCD Controller (CLCDC)
drive signals to interface directly with a variety of color
and monochrome LCD panels.
• LH79524 has 16 LCD Data bits; LH79525 has 12
• Supports single and dual scan color and mono-
22
LCD Data bits.
chrome Super Twisted Nematic (STN) displays with
4- or 8-bit interfaces (LH79524 only)
The DMA Controller provides support for DMA-capa-
– Memory to Memory
– Peripheral to Memory
– Memory to Peripheral
Handles all combinations of byte, half-word or word
The CLCDC provides all the necessary control and
0xFFFFFFFF
0xFFFC0000
0xFFFF1000
0xFFFF0000
0xA0000000
0x80000000
0x60000000
0x40000000
0x20000000
0x00000000
Figure 8. Memory Remap ‘11’
ADVANCED HIGH-PERFORMANCE BUS
ADVANCED PERIPHERAL BUS
EXTERNAL STATIC MEMORY
EXTERNAL SRAM nCS0
16KB INTERNAL SRAM
EXTERNAL SDRAM
PERIPHERALS
PERIPHERALS
REMAP = 11
RESERVED
RESERVED
BOOT ROM
NXP Semiconductors
Rev. 01 — 16 July 2007
LH79525-18
• Supports Thin Film Transistor (TFT) color displays
• Programmable resolution up to 1,024 × 1,024
• 15 gray-level mono, 3,375 color STN, and 64 k color
• 1, 2, or 4 bits-per-pixel (BPP) for monochrome STN
• 1-, 2-, 4-, or 8-BPP palettized color displays for color
• True-color non-palettized, for color STN and TFT
• Programmable timing for different display panels
• 256-entry, 16-bit palette fast-access RAM
• Frame, line and pixel clock signals
• AC bias signal for STN or data enable signal for
• Patented grayscale algorithm
• Interrupt Generation Events
• Dual 16-deep programmable 32-bit wide FIFOs for
ADVANCED LCD INTERFACE
connection to ultra-thin panels that do not include a tim-
ing ASIC. It converts TFT signals from the Color LCD
controller to provide the proper signals, timing and levels
for direct connection to a panel’s Row and Column driv-
ers for AD-TFT, HR-TFT, or any technology of panel that
allows for a connection of this type. The Advanced LCD
Interface peripheral also provides a bypass mode that
allows the LH79524/LH79525 to interface to the built-in
timing ASIC in standard TFT and STN panels.
Synchronous Serial Port (SSP)
nous serial communication with master or slave periph-
eral devices that support protocols for Motorola SPI,
National Semiconductor MICROWIRE, or Texas Instru-
ments Synchronous Serial Interface.
• Master or slave operation
• Programmable clock rate
• Separate transmit FIFO and receive FIFO buffers, 16
• DMA for transmit and receive
• Programmable interface protocols: Motorola SPI,
• Programmable data frame size from 4 to 16 bits
• Independent masking of transmit FIFO, receive FIFO
• Available internal loopback test mode.
TFT support
STN and TFT (1-, 2-, or 4-bit only on LH79525)
TFT panels
buffering incoming data.
bits wide, 8 locations deep
National Semiconductor MICROWIRE, or Texas
Instruments Synchronous Serial Port
and receive overrun interrupts
The Advanced LCD Interface (ALI) allows for direct
The SSP is a master or slave interface for synchro-
Preliminary data sheet
System-on-Chip