LH79525N0Q100A1;55 NXP Semiconductors, LH79525N0Q100A1;55 Datasheet - Page 23

• Manufacturer Part Number: LH79525N0Q100A1;55
• Description: IC ARM7 BLUESTREAK MCU 176LQFP
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7r

Specifications of LH79525N0Q100A1;55

• Package / Case: 176-LQFP
• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 76.2MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LH795
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 50.803 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4333; 935285052557; LH79525N0Q100A1

System-on-Chip
Universal Asynchronous Receiver
Transmitter (UART)
UART0, UART1, and UART2 offer similar functionality
to the industry-standard 16C550. They perform serial-
to-parallel conversion on data received from a periph-
eral device and parallel-to-serial conversion on data
transmitted to the UART. The CPU reads and writes
data and control status information through the AMBA
APB interface. The transmit and receive paths are buff-
ered with internal FIFO memories that support pro-
grammable-service 'trigger levels', and overrun
protection. These FIFO memories enable up to 32
characters to be stored independently in both transmit
and receive modes.
• Programmable bits-per-character (5, 6, 7, or 8)
• Optional nine-bit mode to tag and recognize
• Nine-bit Transmit FIFO and 12-bit Receive FIFO
• Programmable FIFO trigger points
• DMA support for UART0
• Programmable IrDA SIR input/output for each UART
• Separate 16-byte transmit and receive FIFOs to
• Programmable FIFO disabling for 1-byte depth
• Programmable baud rate generator
• Independent masking of transmit FIFO, receive
• False start bit detection
• Line break generation and detection
• Fully-programmable serial interface characteristics:
• IrDA SIR Encode/Decode block, providing:
Vectored Interrupt Controller (VIC)
interrupt request signals from 20 internal and eight
external interrupt sources and applies them, after
masking and prioritization, to the IRQ and FIQ interrupt
inputs of the ARM7TDMI processor core.
Preliminary data sheet
characters as either data or address
reduce CPU interrupts
FIFO, receive timeout and modem status interrupts
The LH79524/LH79525 incorporates three UARTs.
– 5-, 6-, 7-, or 8-bit data word length
– Even-, odd-, or no-parity bit generation and
– 1 or 2 stop bit generation
– Programmable use of IrDA SIR or UART input/
– Supports data rates up to 115.2 kbit/s half-duplex
– Programmable internal clock generator, allowing
– Loopback for testing
The Vectored Interrupt Controller combines the
The Interrupt Controller incorporates a hardware
detection
output
division of the Reference clock in increments of 1
to 512 for low-power mode bit durations.
NXP Semiconductors
Rev. 01 — 16 July 2007
interrupt vector logic with programmable priority for up
to 16 interrupt sources. This logic reduces the interrupt
response time for IRQ type interrupts compared to
solutions using software polling to determine the high-
est priority interrupt source. This significantly improves
the real-time capabilities of the LH79524/LH79525 in
embedded control applications.
• 20 internal and eight external interrupt sources
• IRQ interrupt vector logic for up to 16 channels with
• All of the interrupt channels, with the exception of the
• The Watchdog timer can only generate FIQ interrupt
• External interrupt inputs programmable
programmable priorities
Watchdog Timer interrupt, can be programmed to
generate:
requests
– Individually maskable
– Status accessible for software polling
– FIQ interrupt request
– Non-vectored IRQ interrupt request (software to
– Vectored IRQ interrupt request (up to 16 chan-
– Edge triggered or level triggered
– Rising edge/active HIGH or falling edge/active
The 32 interrupt channels are shown in Table 10.
CHANNEL
poll IRQ source)
nels total)
LOW
10
11
12
13
14
15
16
17
0
1
2
3
4
5
6
7
8
9
Table 10. Interrupt Channels
WDT
Not Used
COMRX (used for debug)
COMTX (used for debug)
Counter/Timer0 Combined
Counter/Timer1 Combined
Counter/Timer2 Combined
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
RTC_ALARM
ACD TSIRQ Combined
ADC Brown Out INTR
INTERRUPT SOURCE
LH79524/LH79525
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