LPC3180FEL320/01,5 NXP Semiconductors, LPC3180FEL320/01,5 Datasheet - Page 25

• Manufacturer Part Number: LPC3180FEL320/01,5
• Description: IC ARM9 MCU 208MHZ 320-LFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3180FEL320/01,5

• Package / Case: 320-LFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 208MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 55
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.3 V
• Data Converters: A/D 3x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 208 MHz
• Operating Supply Voltage: 1.8 V / 3V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM10096
• Minimum Operating Temperature: - 40 C
• Package: 320LFBGA
• Device Core: ARM926EJ-S
• Family Name: LPC3100
• Maximum Speed: 208 MHz
• Number Of Programmable I/os: 55
• Interface Type: I2C/SPI/UART/USB
• On-chip Adc: 3-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1018 - EVAL KIT FOR LP3180568-4063 - KIT DEV LPC3180568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4529; 935286983551

NXP Semiconductors
LPC3180_01_1
Preliminary data sheet
6.24.2 PLLs
6.24.3 Power control and modes
The LPC3180/01 includes three PLLs: one allows boosting the RTC frequency to
13.008896 MHz for use as the primary system clock; one provides the 48 MHz clock
required by the USB block; and one provides the basis for the CPU clock, the AHB bus
clock, and the main peripheral clock.
The first PLL multiplies the 32768 Hz RTC clock by 397 to obtain a 13.008896 MHz clock.
The 397x PLL is designed for low power operation and low jitter. This PLL requires an
external RC loop filter for proper operation.
The other two PLLs accept an input clock from either the main oscillator or the output of
the 397x PLL. The input frequency is multiplied up to a higher frequency, then divided
down to provide the output clock.
The PLL input may initially be divided down by a pre-divider value ‘N’, which may have the
values 1, 2, 3, or 4. This pre-divider can allow a greater number of possibilities for the
output frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the pre-divider
output by a value ‘M’, in the range of 1 through 256. The resulting frequency must be in
the range of 156 MHz to 320 MHz. The multiplier works by dividing the output of a Current
Controlled Oscillator (CCO) by the value of M, then using a phase detector to compare the
divided CCO output to the pre-divider output. The error value is used to adjust the CCO
frequency.
At the PLL output, there is a post-divider that can be used to bring the CCO frequency
down to the desired PLL output frequency. The post-divider value ‘P’, can divide the CCO
output by 1, 2, 4, 8, or 16. The post-divider can also be bypassed, allowing the PLL CCO
output to be used directly. The maximum PLL output frequency that is supported by the
CPU is 208 MHz.
The LPC3180/01 supports three operational modes, two of which are specifically
designed to reduce power consumption. The modes are: Run mode, Direct Run mode,
and Stop mode.
Run mode is the normal operating mode for applications that require the CPU, AHB bus,
or any peripheral function other than the USB block to run faster than the main oscillator
frequency. In Run mode, the CPU can run at up to 208 MHz and the AHB bus can run at
up to 104 MHz.
Direct Run mode allows reducing the CPU and AHB bus rates in order to save power.
Direct Run mode can also be the normal operating mode for applications that do not
require the CPU, AHB bus, or any peripheral function other than the USB block to run
faster than the main oscillator frequency. Direct Run mode is the default mode following
chip reset.
Stop mode causes all CPU and AHB operation to cease, and stops clocks to peripherals
other than the USB block.
Rev. 00.08 — 20 November 2008
16/32-bit ARM microcontroller with external memory interface
LPC3180/01
© NXP B.V. 2008. All rights reserved.
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