ST7FLI49MK1T6 STMicroelectronics, ST7FLI49MK1T6 Datasheet

Page 1

EEPROM, ADC, 8/12-bit timers, and I²C interface Features ■ Memories – 4 Kbytes single voltage extended Flash (XFlash) Program memory with Read-Out Protection In-circuit programming and in-application programming (ICP and IAP) Endurance: 10k write/erase cycles guaranteed Data retention: 20 ...

Page 2

Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

ST7LITE49M 6 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Contents 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

ST7LITE49M 10.7.1 10.7.2 11 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

Contents 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 12 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 7

ST7LITE49M 13.5.1 13.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.6.1 ...

Page 8

List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 9

ST7LITE49M Table 49. ADC register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 10

List of figures List of figures Figure 1. ST7LITE49M general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 11

ST7LITE49M Figure 49. Block diagram of One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 12

List of figures Figure 100. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 13

ST7LITE49M 1 Description The ST7LITE49M is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7LITE49M features Flash memory with byte-by-byte in-circuit programming (ICP) and ...

Page 14

Pin description 2 Pin description Figure 2. 32-pin SDIP package pinout ATPWM2/MCO/PA4(HS) Note 1: Available on 8 Kbytes version only Figure 3. 32-pin LQFP 7x7 package pinout ATPWM1/PA3(HS) ATPWM2/MCO/PA4(HS) ATPWM3/PA5(HS) I2CDATA/PA6(HS) I2CCLK/PA7(HS) 14/188 BREAK/PC7 1 ei2 PA0(HS) 2 ei2 ATIC/PA1(HS) ...

Page 15

ST7LITE49M Legend / Abbreviations for Type input output supply In/Output level: C Output level high sink (on N-buffer only) Port and control configuration: ● Input: float = floating, wpu = ...

Page 16

Pin description Table 2. Device pin description Pin number Pin name 14 18 PB0/AIN0 15 19 PB1/AIN1/CLKIN 16 20 PB2/AIN2 17 21 PB3/AIN3 18 22 PB4/AIN4 19 23 PB5/AIN5 20 24 PB6/AIN6 21 25 PB7/AIN7 22 26 PC0/AIN8 23 27 ...

Page 17

ST7LITE49M 3 Register and memory mapping As shown in Figure registers. The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 128 bytes of data EEPROM and 4 Kbytes of Flash program memory. The RAM ...

Page 18

Register and memory mapping Table 3. Hardware register map Address Block Register label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h PBDR 0004h Port B PBDDR 0005h PBOR 0006h PCDR 0007h Port C PCDDR 0008h PCOR 0009h to 000Bh ...

Page 19

ST7LITE49M Table 3. Hardware register map Address Block Register label 0032h 0033h WDG WDGCR 0034h FLASH FCSR 0035h EEPROM EECSR 0036h ADCCSR 0037h ADC ADCDRH 0038h ADCDRL 0039h 003Ah MCC MCCSR 003Bh RCCR 003Ch SICSR Clock and reset 003Dh AVDTHCR ...

Page 20

Flash programmable memory 4 Flash programmable memory 4.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The ...

Page 21

ST7LITE49M Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In-application programming (IAP) This mode uses ...

Page 22

Flash programmable memory during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up. Figure 5. Typical ICC interface (See Note 3) APPLICATION POWER SUPPLY 22/188 PROGRAMMING TOOL ...

Page 23

ST7LITE49M 4.5 Memory protection There are two different types of memory protection: Read-out protection and Write/Erase Protection which can be applied individually. 4.5.1 Read-out protection Read-out protection, when selected provides a protection against program memory content extraction and against write ...

Page 24

Data EEPROM 5 Data EEPROM 5.1 Introduction The electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 5.2 Main features ...

Page 25

ST7LITE49M 5.3 Memory access The data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in different memory access modes. 5.3.1 Read operation (E2LAT=0) The EEPROM can be read as ...

Page 26

Data EEPROM Figure 8. Data EEPROM write operation ROW DEFINITION Byte 1 E2LAT bit Set by USER application E2PGM bit programming cycle is interrupted (by a reset action), the integrity of the data in memory is not ...

Page 27

ST7LITE49M 5.6 Data EEPROM read-out protection The read-out protection is enabled through an option bit (see When this option is selected, the programs and data stored in the EEPROM memory are protected against Read-out (including a re-write protection). In Flash ...

Page 28

Central processing unit 6 Central processing unit 6.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 6.2 Main features ● 63 basic instructions ● Fast 8-bit by 8-bit multiply ...

Page 29

ST7LITE49M 6.3.1 Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 6.3.2 Index registers (X and Y) In indexed addressing modes, these ...

Page 30

Central processing unit Bit Interrupt mask bit This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts ...

Page 31

ST7LITE49M * Table 4. Interrupt software priority truth table 6.3.5 Stack pointer (SP) Reset value: 01FFh The stack pointer is a 16-bit register which is always pointing to the next free location in the stack. It ...

Page 32

Central processing unit Figure 11. Stack manipulation example CALL Subroutine @ 0180h SP SP PCH @ 01FFh PCL Stack Higher Address = 01FFh Stack Lower Address = 0180h 32/188 PUSH Y POP Y Interrupt Event ...

Page 33

ST7LITE49M 7 Supply, reset and clock management The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. The main features ...

Page 34

Supply, reset and clock management In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. Section 13: Electrical characteristics on page 139 and accuracy of the RC oscillator. ...

Page 35

ST7LITE49M Figure 12. Clock switching Figure 13. Clock management block diagram CK2 CK1 CR9 CR8 Prescaler CLKSEL[1:0] Option bits CLKIN CLKIN CLKIN CLKIN OSC /OSC1 1-16 MHz or 32kHz OSC2 f OSC /32 DIVIDER Set RC/AWU Internal RC Poll AWU_FLAG ...

Page 36

Supply, reset and clock management 7.2 Multi-oscillator (MO) The main clock of the ST7 can be generated by four different source types coming from the multi-oscillator block ( MHz): ● An external source ● 5 different configurations for ...

Page 37

ST7LITE49M Table 6. ST7 clock sources 7.3 Reset sequence manager (RSM) 7.3.1 Introduction The reset sequence manager includes three RESET sources as shown in ● External RESET source pulse ● Internal LVD RESET (low voltage detection) ● Internal WATCHDOG RESET ...

Page 38

Supply, reset and clock management Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is not programmed. For this reason recommended to keep the RESET pin in low state until ...

Page 39

ST7LITE49M 7.3.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low ...

Page 40

Supply, reset and clock management 7.3.5 Internal watchdog reset The reset sequence generated by an internal watchdog counter overflow is shown in Figure 16: Reset sequences Starting from the watchdog counter underflow, the device RESET pin acts as an output ...

Page 41

ST7LITE49M 7.4 System integrity management (SI) The system integrity management block contains the low voltage detector (LVD) and auxiliary voltage detector (AVD) functions managed by the SICSR register. Note: A reset can also be triggered following the detection ...

Page 42

Supply, reset and clock management Figure 17. Low voltage detector vs reset IT+(LVD) V IT-(LVD) RESET Figure 18. Reset and supply management block diagram RESET SEQUENCE RESET 7.4.2 Auxiliary voltage detector (AVD) The ...

Page 43

ST7LITE49M Note: Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD levels are not correlated. Refer to 143 for more details. Figure 19. Using the AVD to monitor ...

Page 44

Supply, reset and clock management 7.5 Register description 7.5.1 Main clock control/status register (MCCSR) Reset value: 0000 0000 (00h Bits 7:2 = Reserved, must be kept cleared. Bit 1 = MCO Main clock out enable bit This ...

Page 45

ST7LITE49M 7.5.3 System integrity (SI) control/status register (SICSR) Reset value: 011x 0x00 (xxh CR1 Bit 7 = Reserved, must be kept cleared Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits These bits, as well as CR[9:2] bits ...

Page 46

Supply, reset and clock management Bit 0 = AVDIE Voltage detector interrupt enable bit This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is ...

Page 47

ST7LITE49M 7.5.5 Clock controller control/status register (CKCNTCSR) Reset value: 0000 1001 (09h Bits 7:4 = Reserved, must be kept cleared. Bit 3 = AWU_FLAG AWU selection bit This bit is set and cleared by hardware ...

Page 48

Interrupts 8 Interrupts 8.1 Introduction The ST7 enhanced interrupt management provides the following features: ● Hardware interrupts ● Software interrupt (TRAP) ● Nested or concurrent interrupt management with flexible interrupt priority and level management: – software programmable ...

Page 49

ST7LITE49M Table 14. Interrupt software priority levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Figure 20. Interrupt processing flowchart RESET RESTORE PC FROM STACK Level Low High PENDING Y ...

Page 50

Interrupts 8.2.1 Servicing pending interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: ● The highest software priority interrupt is serviced, ● If several ...

Page 51

ST7LITE49M Maskable sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and register). ...

Page 52

Interrupts 8.4 Concurrent and nested management The following Figure 22 first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure lowest to the highest: MAIN, IT5, IT4, IT3, IT2, IT1, ...

Page 53

ST7LITE49M 8.5 Description of interrupt registers 8.5.1 CPU CC register interrupt bits Reset value: 111x 1010(xAh Bits I1, I0 Software interrupt priority bits These two bits indicate the current interrupt software priority (see These ...

Page 54

Interrupts The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, ...

Page 55

ST7LITE49M Table 18. ST7LITE49M interrupt mapping Source Number block RESET TRAP 0 AWU 1 AVD Auxiliary voltage detector interrupt 2 ei0 External interrupt 0 (Port A) 3 ei1 External interrupt 1 (Port B) 4 ei2 External interrupt 2 (Port C) ...

Page 56

Interrupts 8.5.3 External interrupt control register (EICR) Reset value: 0000 0000 (00h Bits 7:6 = Reserved, must be kept cleared. Bits 5:4 = IS2[1:0] ei2 sensitivity bits These bits define the interrupt sensitivity for ei2 (Port C) ...

Page 57

ST7LITE49M 9 Power saving modes 9.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see ● Slow ● Wait (and Slow-wait) ● ...

Page 58

Power saving modes 9.2 Slow mode This mode has two targets: ● To reduce power consumption by decreasing the internal clock in the device, ● To adapt the internal clock frequency (f Slow mode is controlled by the SMS bit ...

Page 59

ST7LITE49M Figure 26. Wait mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. ...

Page 60

Power saving modes 9.4.1 Active-halt mode Active-halt mode is the lowest power consumption mode of the MCU with a real-time clock available entered by executing the ‘HALT’ instruction when Active-halt mode is enabled. The MCU can exit Active-halt ...

Page 61

ST7LITE49M Figure 28. Active-halt mode flowchart 1. This delay occurs only if the MCU exits Active-halt mode by means of a RESET. 2. Peripherals clocked with an external clock source can still be active. 3. Only the Lite timer RTC ...

Page 62

Power saving modes Figure 29. Halt timing overview 1. A reset pulse of at least 42 µs must be applied when exiting from Halt mode. Figure 30. Halt mode flowchart 1. WDGHALT is an option bit. See option byte section ...

Page 63

ST7LITE49M Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with ...

Page 64

Power saving modes As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (f a fixed divider and a programmable prescaler controlled by ...

Page 65

ST7LITE49M Figure 33. AWUFH mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific interrupts ...

Page 66

Power saving modes 9.5.1 Register description 9.5.2 AWUFH control/status register (AWUCSR) Reset value: 0000 0000 (00h Bits 7:3 = Reserved Bit 2 = AWUF Auto-wakeup flag This bit is set by hardware when the AWU module generates ...

Page 67

ST7LITE49M 9.5.3 AWUFH prescaler register (AWUPR) Reset value: 1111 1111 (FFh) 7 AWUPR7 AWUPR6 Bits 7:0= AWUPR[7:0] Auto-wakeup prescaler These 8 bits define the AWUPR dividing factor (see Table 21. Configuring the dividing factor AWUPR[7:0 00h 01h ... FEh FFh ...

Page 68

I/O ports 10 I/O ports 10.1 Introduction The I/O ports allow data transfer. An I/O port can contain pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins ...

Page 69

ST7LITE49M Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector ...

Page 70

I/O ports 10.2.3 Alternate functions Many ST7s I/Os have one or more alternate functions. These may include output signals from, or input signals to, on-chip be input/output to which ports. A signal coming from an on-chip peripheral can be output ...

Page 71

ST7LITE49M Table 24. I/O port mode options Configuration mode Floating with/without Interrupt Input Pull-up with Interrupt Output Open-drain (logic level) 1. Off means implemented not activated, On means implemented and activated. Table 25. I/O port configuration PAD PAD PAD 1. ...

Page 72

I/O ports 10.2.4 Analog alternate function Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected ...

Page 73

ST7LITE49M 10.6 Interrupts The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction). Table 27. Description of interrupt events ...

Page 74

I/O ports Table 30. PC3 pin (continued) Table 31. Port configuration Port Pin name Port A Port B Port C Table 32. I/O port register mapping and reset values Address Register 7 label (Hex.) PADR MSB 0000h Reset value 0 ...

Page 75

ST7LITE49M 11 On-chip peripherals 11.1 Watchdog timer (WDG) 11.1.1 Introduction The watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon ...

Page 76

On-chip peripherals The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored ...

Page 77

ST7LITE49M 11.1.6 Register description Control register (WDGCR) Reset value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog ...

Page 78

On-chip peripherals 11.2 Dual 12-bit autoreload timer 11.2.1 Introduction The 12-bit autoreload timer can be used for general-purpose timing functions based on one or two free-running 12-bit upcounters with an input capture register and four PWM output channels. ...

Page 79

ST7LITE49M Figure 37. Single timer mode (ENCNTR2=0) ATIC Edge Detection Circuit 12-Bit Autoreload register 1 Clock Control Figure 38. Dual timer mode (ENCNTR2=1) Edge Detection Circuit ATIC 12-Bit Autoreload register 1 12-Bit Autoreload register 2 Control LTIC 12-bit Input Capture ...

Page 80

On-chip peripherals 11.2.3 Functional description PWM mode This mode allows up to four pulse width modulated signals to be generated on the PWMx output pins. ● PWM frequency The four PWM signals can have the same frequency (f frequencies. This ...

Page 81

ST7LITE49M The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case. ● Polarity inversion The polarity bits can be used to invert any of the four output ...

Page 82

On-chip peripherals Figure 41. PWM signal from 0% to 100% duty cycle f COUNTER COUNTER DCRx=000h DCRx=FFDh DCRx=FFEh DCRx=000h Dead time generation A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is required for ...

Page 83

ST7LITE49M Figure 42. Dead time generation CK_CNTR1 CNTR1 PWM 0 PWM 1 PWM 0 PWM 1 In the above example, when the DTE bit is set: ● PWM goes low at DCR0 match and goes high at ATR1+Tdt ● PWM1 ...

Page 84

On-chip peripherals When a break function is activated (BA bit =1 and BREN1/BREN2 =1): ● The break pattern (PWM[3:0] bits in the BREAKCR) is forced directly on the PWMx output pins if respective OEx is set. (after the inverter). ● ...

Page 85

ST7LITE49M Figure 44. Block diagram of output compare mode (single timer) DCRx PRELOAD DUTY CYCLE REG0/1/2/3 (ATCSR2) TRAN1 (ATCSR) OVF CNTR1 Input capture mode The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter ...

Page 86

On-chip peripherals Figure 46. Input capture timing diagram f COUNTER COUNTER1 01h ATIC PIN ICF FLAG Long range input capture Pulses that last more than 8 µs can be measured with an accuracy of 4 µ MHz in ...

Page 87

ST7LITE49M Since the input capture flags (ICF) for both timers (AT4 timer and LT timer) are set when signal transition occurs, software must mask one interrupt by clearing the corresponding ICIE bit before setting the ICS bit. If the ICS ...

Page 88

On-chip peripherals Figure 48. Long range input capture timing diagram f OSC/32 TB Counter1 F9h CNTR1 LTIC LTICR ATICRH ATICRL 88/188 00h LT1 F9h 00h ATH1 & ATL1 00h LT1 0h ATH1 00h ATL1 Doc ID 13562 ...

Page 89

ST7LITE49M One-pulse mode One-pulse mode can be used to control PWM2/3 signal with an external LTIC pin. This mode is available only in Dual Timer mode i.e. only for CNTR2, when the OP_EN bit in PWM3CSR register is set. One-pulse ...

Page 90

On-chip peripherals How to enter One-pulse mode The steps required to enter One-pulse mode are the following: 1. Load ATR2H/ATR2L with required value. 2. Load DCR3H/DCR3L for PWM3. ATR2 value must be greater than DCR3. 3. Set OP3 in PWM3CSR ...

Page 91

ST7LITE49M Figure 51. Dynamic DCR2/3 update in One-pulse mode f counter2 CNTR2 LTIC FORCE2 TRAN2 DCR2/3 PWM2/3 Force update In order not to wait for the counter programmable counter which when set, make the counters start with the overflow value, ...

Page 92

On-chip peripherals 11.2.4 Low power modes Table 35. Effect of low power modes on autoreload timer Mode Wait Halt 11.2.5 Interrupts Table 36. Description of interrupt events Interrupt event Overflow Event AT4 IC Event Overflow Event2 Note: The AT4 IC ...

Page 93

ST7LITE49M Bits 4:3 = CK[1:0] Counter clock selection bits These bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. Table 37. Counter clock selection Bit 2 = ...

Page 94

On-chip peripherals Bits 11:0 = CNTR1[11:0] Counter value This 12-bit register is read by software and cleared by hardware after a reset. The counter CNTR1 increments continuously as soon as a counter clock is selected. To obtain the 12-bit value, ...

Page 95

ST7LITE49M PWMX control status register (PWMxCSR) Reset value: 0000 0000 (00h Bits 7:4= Reserved, must be kept cleared. Bit 3 = OP_EN One-pulse mode enable bit This bit is read/write by software and cleared by hardware after ...

Page 96

On-chip peripherals Bit 6 = BREDGE Break input edge selection bit This bit is read/write by software and cleared by hardware after reset. It selects the active level of Break signal. 0: Low level of Break selected as active level ...

Page 97

ST7LITE49M Input capture register high (ATICRH) Reset value: 0000 0000 (00h Bits 15:12 = Reserved. Input capture register low (ATICRL) Reset value: 0000 0000 (00h) 7 ICR7 ICR6 Bits 11:0 = ICR[11:0] Input capture data. This is a ...

Page 98

On-chip peripherals Timer control register 2 (ATCSR2) Reset value: 0000 0011 (03h) 7 FORCE2 FORCE1 Bit 7 = FORCE2 Force counter 2 overflow bit This bit is read/set by software. When set, it loads FFFh in the CNTR2 register. It ...

Page 99

ST7LITE49M Bit 1= TRAN2 Transfer enable2 bit This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR2. It allows the value of the Preload DCRx ...

Page 100

On-chip peripherals Dead time generator register (DTGR) Reset value: 0000 0000 (00h) 7 DTE DT6 Bit 7 = DTE Dead time enable bit This bit is read/write by software. It enables a dead time generation on PWM0/PWM1 Dead ...

Page 101

ST7LITE49M Table 38. Register mapping and reset values (continued) Add. Register 7 (Hex) label DCR0L DCR7 001C Reset value 0 DCR1H 001D 0 Reset value DCR1L DCR7 001E Reset value 0 DCR2H 001F 0 Reset value DCR2L DCR7 0020 Reset ...

Page 102

On-chip peripherals 11.3 Lite timer 2 (LT2) 11.3.1 Introduction The Lite timer can be used for general-purpose timing functions based on two free- running 8-bit upcounters and an 8-bit input capture register. 11.3.2 Main features ● Real-time clock ...

Page 103

ST7LITE49M 11.3.3 Functional description Timebase counter 1 The 8-bit value of counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from frequency of f counter rolls over from F9h to ...

Page 104

On-chip peripherals 11.3.4 Low power modes Table 39. Effect of low power modes on Lite timer 2 Mode Slow Wait Active-halt Halt 11.3.5 Interrupts Table 40. Description of interrupt events Interrupt event Timebase 1 Event Timebase 2 Event IC Event ...

Page 105

ST7LITE49M Bit 0 = TB2F Timebase 2 Interrupt flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect Counter 2 overflow 1: A Counter 2 overflow ...

Page 106

On-chip peripherals Bit 6 = ICF Input capture flag This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value Input Capture 1: An ...

Page 107

ST7LITE49M Table 41. Lite timer register mapping and reset values (continued) Address Register 7 label (Hex.) LTCSR1 ICIE 0F Reset value 0 LTICR ICR7 10 Reset value ICF TB TB1IE TB1F ICR6 ICR5 ...

Page 108

On-chip peripherals 2 11 bus interface (I 11.4.1 Introduction 2 The I C Bus Interface serves as an interface between the microcontroller and the serial I bus. It provides both multimaster and slave functions, and controls all I ...

Page 109

ST7LITE49M Mode selection The interface can operate in the four following modes: ● Slave transmitter/receiver ● Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and ...

Page 110

On-chip peripherals 2 When the I C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. 2 When the I ...

Page 111

ST7LITE49M 11.4.4 Functional description Refer to the CR, SR1 and SR2 registers default the I C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface ...

Page 112

On-chip peripherals Closing slave communication After the last data byte is transferred a stop condition is generated by the master. The interface detects this condition and sets: EVF and STOPF bits with an interrupt if the ITE bit is set. ...

Page 113

ST7LITE49M Master mode To switch from default Slave mode to Master mode a Start condition generation is needed. Start condition Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit ...

Page 114

On-chip peripherals Master transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the ...

Page 115

ST7LITE49M Figure 57. Transfer sequencing 7-bit slave receiver S Address A 7-bit slave transmitter S Address A 7-bit master receiver S Address A EV5 7-bit master transmitter S Address A EV5 10-bit slave receiver S Header A 10-bit slave transmitter ...

Page 116

On-chip peripherals subsequent EV4 is not seen. 6. EV4: EVF=1, STOPF=1, cleared by reading SR2 register. 7. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. 8. EV6: EVF=1, cleared by reading SR1 register followed by ...

Page 117

ST7LITE49M 11.4.7 Register description control register (I2CCR) Reset value: 0000 0000 (00h Bits 7:6 = Reserved. Forced hardware. Bit Peripheral Enable bit This bit is set and cleared ...

Page 118

On-chip peripherals Bit 1 = STOP Generation of a Stop condition bit This bit is set and cleared by software also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled ...

Page 119

ST7LITE49M status register 1 (I2CSR1) Reset value: 0000 0000 (00h) 7 EVF ADD10 Bit 7 = EVF Event flag This bit is set by hardware as soon as an event occurs cleared by software reading ...

Page 120

On-chip peripherals Bit 3 = BTF Byte transfer finished bit This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE= cleared by software reading SR1 register followed ...

Page 121

ST7LITE49M status register 2 (I2CSR2) Reset value: 0000 0000 (00h Bits 7:5 = Reserved. Forced hardware. Bit Acknowledge failure bit This bit is set by hardware when no ...

Page 122

On-chip peripherals Note bus error occurs, a Stop or a repeated Start condition should be generated by the Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication Bit 0 = GCAL General ...

Page 123

ST7LITE49M own address register (I2COAR1) Reset value: 0000 0000 (00h) 7 ADD7 ADD6 ● In 7-bit addressing mode Bits 7:1 = ADD[7:1] Interface address. These bits define the I interface. They are not cleared when the interface ...

Page 124

On-chip peripherals 2 Table 45 register mapping and reset values Address Register 7 label (Hex.) I2CCR 0064h Reset 0 value I2CSR1 EVF 0065h Reset 0 value I2CSR2 0066h Reset 0 value I2CCCR FM/SM 0067h Reset 0 value I2COAR1 ...

Page 125

ST7LITE49M 11.5 10-bit A/D converter (ADC) 11.5.1 Introduction The on-chip analog to digital converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to ...

Page 126

On-chip peripherals Figure 59. ADC block diagram f CPU AIN0 AIN1 AINx Digital A/D conversion result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does ...

Page 127

ST7LITE49M Configuring the A/D conversion The analog input ports must be configured as input, no pull-up, no interrupt (see I/O ports). Using these pins as analog inputs does not affect the ability of the port to be read as a ...

Page 128

On-chip peripherals 11.5.6 Register description Control/status register (ADCCSR) Reset value: 0000 0000 (00h) 7 EOC SPEED Read only Bit 7 = EOC End of conversion bit This bit is set by hardware cleared by hardware when software reads ...

Page 129

ST7LITE49M Data register high (ADCDRH) Reset value: xxxx xxxx (xxh Bits 7:0 = D[9:2] MSB of analog converted value ADC control/data register low (ADCDRL) Reset value: 0000 00xx (0xh Bits 7:4 = Reserved. Forced ...

Page 130

Instruction set 12 Instruction set 12.1 ST7 addressing modes The ST7 core features 17 different addressing modes which can be classified in seven main groups: Table 50. Description of addressing modes Addressing mode The ST7 instruction set is designed to ...

Page 131

ST7LITE49M Table 51. ST7 addressing mode overview (continued) Mode Long Indirect Indexed Relative Direct Relative Indirect Bit Direct Bit Indirect Bit Direct Relative Bit Indirect Relative 1. At the time the instruction is executed, the Program Counter (PC) points to ...

Page 132

Instruction set Table 52. Instructions supporting inherent addressing mode (continued) SLL, SRL, SRA, RLC, RRC 12.1.2 Immediate mode Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. Imm Table 53. Instructions ...

Page 133

ST7LITE49M Indexed mode (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 Indirect modes (short, long) The required data byte to do the operation is found by its memory ...

Page 134

Instruction set Table 54. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes (continued) Short instructions only SLL, SRL, SRA, RLC, RRC 12.1.7 Relative modes (direct, indirect) This addressing mode is used to modify the PC register value by ...

Page 135

ST7LITE49M 12.2 Instruction groups The ST7 family devices use an instruction set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Table 56. ST7 instruction set Instructions Load and Transfer ...

Page 136

Instruction set 12.2.1 Illegal opcode reset In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented: a reset is generated if the code to be executed does not correspond to ...

Page 137

ST7LITE49M Table 57. Illegal opcode detection (continued) Mnemo Description JRPL Jump (plus) JREQ Jump (equal) JRNE Jump (not equal) JRC Jump JRNC Jump if ...

Page 138

Instruction set Table 57. Illegal opcode detection (continued) Mnemo Description WFI Wait for interrupt XOR Exclusive OR 138/188 Function/Example Dst XOR M A Doc ID 13562 Rev 3 ST7LITE49M Src ...

Page 139

ST7LITE49M 13 Electrical characteristics 13.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 13.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage ...

Page 140

Electrical characteristics Figure 61. Pin input voltage 13.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these ...

Page 141

ST7LITE49M Table 59. Current characteristics Symbol I VDD I VSS I IO (2)(3) I INJ(PIN) ΣI (2) INJ(PIN) 1. All power (V ) and ground ( must never be exceeded. This is implicitly insured if V INJ(PIN) ...

Page 142

Electrical characteristics 13.3 Operating conditions 13.3.1 General operating conditions T = -40 to +125 °C unless otherwise specified. A Table 61. General operating conditions Symbol CPU clock frequency CPU Figure 62. f CPU f CPU FUNCTIONALITY NOT ...

Page 143

ST7LITE49M 2. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application recommended to pull V circuit example in 13.3.3 Auxiliary voltage detector (AVD) thresholds T = -40 ...

Page 144

Electrical characteristics 13.3.5 Internal RC oscillator To improve clock stability and frequency accuracy recommended to place a decoupling capacitor, typically 100 nF, between the V device Internal RC oscillator calibrated at 5.0 V The ST7 internal clock can ...

Page 145

ST7LITE49M Table 66. Internal RC oscillator characteristics (3.3 V calibration) Symbol Parameter Accuracy of internal ACC RC oscillator with RC 1) RCCR=RCCR1 RC oscillator setup t su(RC) time 1. See Section 7.1.1: Internal RC oscillator 2. Tested in production at ...

Page 146

Electrical characteristics Figure 65. Accuracy voltage at 4 different ambient temperatures ( Figure 66. Accuracy voltage at 4 different ambient temperatures (RC at 3.3 V) 146/188 2.2 2.0 1.8 1.6 1.4 ...

Page 147

ST7LITE49M 13.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must ...

Page 148

Electrical characteristics Figure 67. Typical I Figure 68. Typical I Figure 69. Typical I 148/188 in Run mode vs CPU 6.0 2MHz 5.0 4MHz 4.0 8MHz 3.0 2.0 1.0 0.0 Vdd [V] in WFI vs CPU ...

Page 149

ST7LITE49M Figure 70. Typical I Figure 71. Typical I in Slow-wait mode vs CPU 2 MHz 0.6 0.5 4 MHz 0.4 8 MHz 0.3 0.2 0.1 0 Vdd [V] vs. temperature and f ...

Page 150

Electrical characteristics 13.4.2 On-chip peripherals Table 68. On-chip peripheral characteristics Symbol I 12-bit auto-reload timer supply current DD(AT) I DD(I2C) I ADC supply current when converting DD(ADC) 1. Data based on a differential I running in PWM mode at f ...

Page 151

ST7LITE49M Table 70. SCL frequency (multimaster I f CPU f SCL =3.3 kΩ R =4.7 kΩ 400 NA NA 300 NA NA 200 84h 84h 100 11h 11h 50 25h 25h 20 ...

Page 152

Electrical characteristics Table 72. External clock source characteristics Symbol V or OSC1H V CLKIN_H V or OSC1L V CLKIN_L t w(OSC1H w(CLKINH) t w(OSC1L w(CLKINL r(OSC1) or r(CLKIN f(OSC1) or f(CLKIN) I ...

Page 153

ST7LITE49M 13.6.2 Crystal and ceramic resonator oscillators The ST7 internal clock can be supplied with ten different crystal/ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, ...

Page 154

Electrical characteristics Figure 73. Typical application with a crystal or ceramic resonator WHEN RESONATOR WITH INTEGRATED CAPACITORS 154/188 Resonator Doc ID 13562 Rev 3 ST7LITE49M OSC1 ST7LITE49M OSC2 OSC ...

Page 155

ST7LITE49M 13.7 Memory characteristics T = -40 °C to 125 °C, unless otherwise specified. A Table 76. RAM and hardware registers characteristics Symbol V Data retention mode RM 1. Minimum V supply voltage without losing data stored in RAM (in ...

Page 156

Electrical characteristics 13.8 EMC (electromagnetic compatibility) characteristics Susceptibility tests are performed on a sample basis during product characterization. 13.8.1 Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling two LEDs through I/O ports), the product ...

Page 157

ST7LITE49M 13.8.2 EMI (electromagnetic interference) Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J ...

Page 158

Electrical characteristics Table 82. Electrical sensitivities Symbol LU 13.9 I/O port pin characteristics 13.9.1 General characteristics Subject to general operating conditions for V Table 83. General characteristics Symbol Parameter V Input low level voltage IL V Input high level voltage ...

Page 159

ST7LITE49M Figure 74. Two typical applications with unused I/O pin kΩ 1. During normal operation the ICCCLK pin must be pulled-up, internally or externally (external pull- kΩ mandatory in noisy environment). This is to avoid ...

Page 160

Electrical characteristics 13.9.2 Output driving current Subject to general operating conditions for V Table 84. Output driving current characteristics Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure ...

Page 161

ST7LITE49M Figure 77. Typical V Figure 78. Typical V Figure 79. Typical 2.4 V (standard 1400 -40°C 1200 25°C 85°C 1000 125°C 800 600 400 200 Iload [mA ...

Page 162

Electrical characteristics Figure 80. Typical V Figure 81. Typical V Figure 82. Typical V 162/188 2.4 V (high sink 1200 -40°C 1000 25°C 85°C 800 125°C 600 400 200 ...

Page 163

ST7LITE49M Figure 83. Typical V 490 440 390 340 290 240 190 140 Figure 84. Typical V 1540 1340 1140 940 740 540 340 140 2.4 2.6 2.8 Figure 85. Typical V 120 110 100 ...

Page 164

Electrical characteristics Figure 86. Typical V 540 490 440 390 340 290 240 190 140 Figure 87. Typical V 1040 940 840 740 640 540 440 340 240 140 Figure 88. Typical V 164/188 ...

Page 165

ST7LITE49M Figure 89. Typical V Figure 90. Typical (high sink 1800 -40°C 1600 25°C 1400 85°C 1200 125°C 1000 800 600 400 200 Iload[mA] ...

Page 166

Electrical characteristics Figure 91. Typical V Figure 92. Typical V Figure 93. Typical V 166/188 -V vs 2.4 V (standard 800 -40°C 700 25°C 600 85°C 500 125°C 400 300 200 100 ...

Page 167

ST7LITE49M Figure 94. Typical V Figure 95. Typical (high sink 800 700 600 500 400 300 200 100 0 2.4 2.8 3.2 3.6 4 Vdd [V] -V ...

Page 168

Electrical characteristics 13.10 Control pin characteristics 13.10.1 Asynchronous RESET pin T = -40 to 125 °C, unless otherwise specified. A Table 85. Asynchronous RESET pin characteristics Symbol Parameter V Input low level voltage IL V Input high level voltage IH ...

Page 169

ST7LITE49M Figure 96. RESET pin protection when LVD is enabled Required EXTERNAL RESET 0.01μF 1. The reset network protects the device against parasitic resets. The output of the external reset circuit must have an open-drain output to drive the ST7 ...

Page 170

Electrical characteristics Figure 97. RESET pin protection when LVD is disabled USER EXTERNAL RESET CIRCUIT Required 1. The reset network protects the device against parasitic resets. The output of the external reset circuit must have an open-drain output to drive ...

Page 171

ST7LITE49M Figure 98. Typical application with ADC R AIN V AIN Table 87. ADC accuracy with V Symbol ( Total unadjusted error Differential linearity error Integral ...

Page 172

Electrical characteristics Figure 99. ADC accuracy characteristics Digital Result 1023 1022 1LSB IDEAL 1021 172/188 V V – ------------------------------- - 1024 (2) E ...

Page 173

ST7LITE49M 14 Device configuration and ordering information This device is available for production in user programmable version (Flash). ST7LITE49M XFlash devices are shipped to customers with a default program memory content (FFh). 14.1 Option bytes The two option bytes allow ...

Page 174

Device configuration and ordering information This option bit determines if a reset is generated when entering Halt mode while the Watchdog is active reset generation when entering Halt mode 1: Reset generation when entering Halt mode 14.1.2 Option ...

Page 175

ST7LITE49M Table 93. Configuration of sector size Sector 0 Size 0. Bit 1 = FMP_R Read-out protection Read-out protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Erasing ...

Page 176

... Development tools Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. ...

Page 177

... For additional ordering codes for spare parts and accessories, refer to the online product selector at www.st.com/mcu. Table 94. Development tool order codes for the ST7LITE49M family MCU ST7FLI49MK1T6 ST7FLI49MK1B6 1. Contact local ST sales office for sales types. 2. USB connection to PC. 3. Available from ST or from Raisonance, www.raisonance.com. ...

Page 178

Device configuration and ordering information 14.4 ST7 application notes Table 95. ST7 application notes Identification AN1658 Serial numbering implementation AN1720 managing the Read-Out Protection in Flash microcontrollers AN1755 A high resolution/precision thermometer using ST7 and NE555 AN1756 Choosing a DALI ...

Page 179

ST7LITE49M Table 95. ST7 application notes (continued) Identification AN1276 BLDC motor start routine for the ST72141 microcontroller AN1321 Using the ST72141 motor control MCU in Sensor mode AN1325 Using the ST7 USB low-speed firmware V4.x AN1445 Emulated 16-bit slave SPI ...

Page 180

Device configuration and ordering information Table 95. ST7 application notes (continued) Identification AN1014 How to minimize the ST7 power consumption AN1015 Software techniques for improving microcontroller EMC performance AN1040 Monitoring the Vbus signal for USB self-powered devices AN1070 ST7 checksum ...

Page 181

ST7LITE49M Table 95. ST7 application notes (continued) Identification AN1635 ST7 customer ROM code release information AN1754 Data logging program for testing ST7 applications via ICC AN1796 Field updates for Flash memory based ST7 applications using a PC comm port AN1900 ...

Page 182

Package mechanical data 15 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: ...

Page 183

ST7LITE49M Table 96. 32-pin plastic dual in-line package, shrink 400-mil width, (mechanical data (continued) Dim Values in inches are converted from mm and rounded to 4 decimal digits. Figure 102. 32-pin low profile quad flat package (7x7), ...

Page 184

Package mechanical data Table 97. 32-pin low profile quad flat package (7x7), package mechanical data Dim Values in inches are converted from mm and rounded to 4 decimal digits. 15.1 Thermal characteristics Table 98. Thermal characteristics Symbol ...

Page 185

ST7LITE49M 16 Revision history Table 99. Document revision history Date 01-Jun-2007 13-July-2007 Revision 1 Initial release. Document reformatted and status updated to Full Datasheet. Table 5. EEPROM register mapping and reset values removed. Section 7.2.3: Internal RC oscillator threshold selection ...

Page 186

Revision history Table 99. Document revision history (continued) Date 13-Nov-2009 186/188 Revision CKIN replaced by CLKIN in Reset configuration of each pin shown in bold in In Table 2 on page 15: OSC1 replaced by OSC1/CLKIN Modified reset configuration for ...

Page 187

... ST7LITE49M Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...