ST7FLI49MK1T6 STMicroelectronics, ST7FLI49MK1T6 Datasheet - Page 82

• Manufacturer Part Number: ST7FLI49MK1T6
• Description: MCU 8BIT SGL VOLT FLASH 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLI49MK1T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLI4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

On-chip peripherals
Note:
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Figure 41. PWM signal from 0% to 100% duty cycle
Dead time generation
A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is
required for half-bridge driving where PWM signals must not be overlapped. The non-
overlapping PWM0/PWM1 signals are generated through a programmable dead time by
setting the DTE bit.
DTGR[7:0] is buffered inside so as to avoid deforming the current PWM cycle. The DTGR
effect will take place only after an overflow.
Dead time is generated only when DTE=1 and DT[6:0]
PWM output signals will be at their reset state.
Half Bridge driving is possible only if polarities of PWM0 and PWM1 are not inverted, i.e. if
OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be
generated.
Dead time generation does not work at 1ms timebase.
DCRx=FFDh
DCRx=FFEh
DCRx=000h
DCRx=000h
COUNTER
f
COUNTER
FFDh
Dead time
FFEh
Doc ID 13562 Rev 3
ATR= FFDh
FFFh
=
DT 6:0
[
FFDh
]
×
Tcounter1
≠
FFEh
0
.
If DTE is set and DT[6:0]=0,
FFFh
FFDh
ST7LITE49M
FFEh
t