Z86E0208HSG1925 Zilog, Z86E0208HSG1925 Datasheet - Page 43

• Manufacturer Part Number: Z86E0208HSG1925
• Description: IC Z8 .5K OTP 8MHZ 20-SSOP
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E0208HSG1925

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 14
• Program Memory Size: 512B (512 x 8)
• Program Memory Type: OTP
• Ram Size: 61 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Processor Series: Z86E02x
• Core: Z8
• Data Bus Width: 8 bit
• Data Ram Size: 61 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3946; Z86E0208HSG1925

PS014802-0903
Resistor (R)
1. A = Standard mode frequency
2. B = Low EMI mode frequency
5 KΩ
2 KΩ
1 KΩ
HALT Mode
STOP Mode
Table 16. Typical Frequency (MHz) vs. RC Values V
Note:
Note:
12.5
This instruction turns off the internal CPU clock but not the crystal oscillation. The
counter/timers and external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain active.
The device is recovered by interrupts, either externally or internally generated. An
interrupt request must be executed (enabled) to exit HALT mode. After the inter-
rupt service routine, the program continues from the instruction after the HALT.
This instruction turns off the internal clock and external crystal oscillation and
reduces the standby current to 10 A. The STOP mode is released by a RESET
through a Stop-Mode Recovery (pin P27). A LOW INPUT condition on P27
releases the STOP mode. Program execution begins at location 000C (Hex).
Refer to the Watch Dog Timer (WDT) section for information relating to WDT
wakeup out of Stop Mode. However, when P27 is used to release STOP mode,
the I/O port mode registers are not reconfigured to their default POWER-ON con-
ditions. Thus the I/O, configured as output when the STOP instruction was exe-
cuted, is prevented from glitching to an unknown state. To use the P27 release
approach with STOP mode, use the following instruction:
7.6
17
A
33 pF
LD
NOP
STOP
Note: X = Dependent on user’s application.
On the C12 ICEBOX, the IRQ3 does not wake the device out of
HALT Mode.
The device can be recovered by a WDT timeout. The WDT
reset in HALT Mode generates a full reset similar to the Normal
run mode (not STOP Mode).
1.6
2.3
3.1
B
P2M, #1XXX XXXXB
3.6
8.5
13
A
56 pF
1.0
1.7
2.5
B
Load Capacitor
General-Purpose OTP MCU with 14 I/O Lines
2.3
4.1
9.5
A
100 pF
CC
= 5.0 V @ 25°C (Continued)
0.7
1.3
1.8
B
0.66
0.28
1.2
A
0.001 µF
Z86E02 SL 1925
0.14
0.27
0.42
B
37