Z86E0208HSG1925 Zilog, Z86E0208HSG1925 Datasheet - Page 45

• Manufacturer Part Number: Z86E0208HSG1925
• Description: IC Z8 .5K OTP 8MHZ 20-SSOP
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E0208HSG1925

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 14
• Program Memory Size: 512B (512 x 8)
• Program Memory Type: OTP
• Ram Size: 61 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Processor Series: Z86E02x
• Core: Z8
• Data Bus Width: 8 bit
• Data Ram Size: 61 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3946; Z86E0208HSG1925

PS014802-0903
Software Work Around on the Z86CCP01ZEM Emulator
to Emulate the Software WDT Running in HALT Mode
Note:
Op Code WDT (5Fh)
The first time Op Code 5Fh is executed, the WDT is enabled; subsequent execu-
tion clears the WDT counter. This clearing of the counter must be performed at
least every T
erated reset is the same as a power-on reset of T
The software enabled WDT does not run in STOP mode.
On the CCP emulator, a software workaround must be used to emulate the soft-
ware WDT. This workaround follows.
Op Code WDH (4Fh)
When this instruction is executed it enables the WDT during HALT. If not, the WDT
stops when entering HALT. This instruction does not clear the counters – it just
makes it possible to operate the WDT during HALT mode. A WDH instruction exe-
cuted without executing WDT (5Fh) yields no effect.
Permanent WDT
Selecting the hardware-enabled Permanent WDT option bit automatically enables
the WDT upon exiting reset. The permanent WDT always runs in HALT mode and
STOP mode, and it cannot be disabled.
On the CCP emulator, a software workaround must be used to
enable the software in HALT Mode/STOP Mode or hardware-
enabled WDT. This workaround follows.
SWFIXSWDT:
SWFIXSWDT:
WDT
; otherwise, the WDT times out and generates a reset. The gen-
PUSH RP
LD RP, #0Fh
LD R15,#00000101B
POP RP
PUSH RP
LD RP, #0Fh
LD R15,#00000101B
POP RP
General-Purpose OTP MCU with 14 I/O Lines
PQR
, plus 18 crystal clock cycles.
Z86E02 SL 1925
39